System for performing input and output operations to and from a processor

• US 6,125,412 A
• Filed: 04/09/1993
• Issued: 09/26/2000
• Est. Priority Date: 09/19/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Chips and Technologies LLC (Intel Corporation)
• Inventors: Picard, James A., Jones, Morris E. Jr.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/046,109
• Time in Patent Office: 2,727 Days
• Field of Search: 710/15-21, 710/36-51, 710/58-61, 710/260-269, 713/300-340, 713/500-502
• US Class Current: 710/48
• CPC Class Codes: G06F 13/105 where the programme performs an input/output emulation function
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A system for performing input and output operations to and from a processor in which interrupts for I/O operations are conditionally generated internally rather than externally by (Super State™) microcode residing in a separate address space in memory in an area protected from the user. A (superblock) register in the processor points to the Super State area in memory. If the Super State mode is turned on, an interrupt is generated within the processor whenever the control table allows. The interrupt directs the processor to the register and hence to the Super State code. By way of example, the Super State code controls power and access to the port, decides whether to put the interrupt in memory and emulate the I/O, and counts access to the port. The invention provides a processor with the flexibility of performing I/O operations to and from memory and/or to a peripheral or to trap an interrupt into a new operating environment for device emulation. Device emulation and monitoring is allowed without considerable program overhead. The invention provides a powerful, efficient I/O control system which can change or adapt in response the changing demands of an application program.

Claims

1. A system including a microprocessor having a memory, a means for executing a series of instructions, and a plurality of input/output ports each capable of connection to an input/output device, said series of instructions including input and output instructions, the system comprising:

instruction means within said microprocessor for entering a super state mode of operation from a normal mode of operation;

input/output control code stored in said memory beginning at a particular address, said input/output control code for controlling input and output between said microprocessor and said ports;

a super state block register within said microprocessor for storing said particular address;

instruction means within said microprocessor for generating an interrupt each time said microprocessor encounters an input or an output instruction in said series of instructions while in said super state mode, said interrupt causing said microprocessor to access said super state block register and execute said input/output control code.

2. The system of claim 1, wherein said normal mode of operation is a first power consumption mode and said super state mode of operation is a second power consumption mode.

3. The system of claim 1, wherein said memory further comprises input/output tables containing control information indicating when the input/output device should be turned on, said input/output control code controlling access to said control information.

4. The system of claim 3, further comprising:

a port reference counter in said memory, said port reference counter having a count associated with an input/output device, said count being incremented every time the input/output port is either read or written.

5. A method for managing the input and output operations of a battery powered computer, said computer including a microprocessor having a memory, a means for entering a super state mode of operation from a normal mode of operation, a plurality of input/output ports each capable of connection to an input/output device, input/output control code in said memory for controlling power to an input/output device and for controlling input and output between said microprocessor and said ports, and means for executing a series of instructions including input and output instructions, the method comprising:

entering said super state mode of operation from said normal mode of operation;

executing said series of instructions; and

generating an interrupt within said microprocessor each time said microprocessor encounters an input or an output instruction in said series of instructions while in said super state mode, said interrupt causing said microprocessor to execute said input/output control code each time said microprocessor encounters an input or an output instruction in said series of instructions.

6. The method of claim 5, wherein said memory further comprises input/output tables containing control information, the method further comprising:

accessing said control information in said input/output tables;

controlling power to an input/output device as indicated by said control information.

7. The method of claim 5, wherein said memory further comprises input/output tables containing control information, the method further comprising:

accessing said control information in said input/output tables;

writing to memory if said instruction is an output instruction and said input/output device is powered off or sleeping.

8. The method of claim 5, wherein said memory further comprises a port reference counter having a count associated with the input/output device, the method further comprising:

incrementing said count every time the input/output port is either read or written; and

powering off the input/output device if said count approaches a static level.

9. The method of claim 5, wherein said memory further comprises a port reference counter having a count associated with the input/output device, the method further comprising:

incrementing said count every time the input/output port is either read or written; and

slowing down the CPU clock if said count approaches a static level.