Method and device for communicating across a chip boundary including a serial-parallel data packet converter having flow control logic

• US 6,125,416 A
• Filed: 10/29/1997
• Issued: 09/26/2000
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Ltd (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Ltd (STMicroelectronics NV)
• Inventors: Warren, Robert
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/960,757
• Time in Patent Office: 1,063 Days
• Field of Search: 395/891, 714/30, 712/38, 371/22.32, 710/71
• US Class Current: 710/71
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry. The serial to parallel data packet converter is operable to read the packet identifier to determine the length of serial packets which are input through the port and to convert them into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system. The serial to parallel converter further includes flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry. In this device, the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and the parallel data causes the functional circuitry to execute an operation dependent on the information contained in the serial packets from which it has been converted.

Claims

1. A single chip integrated circuit device comprising:

a bus system for effecting communication of parallel data on chip;

functional circuitry connected to said bus system for executing an operation in response to parallel data received from said bus system;

an external port comprising a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device, said serial data packets each including a packet identifier indicating the length of the data packet and information defining an operation to be executed by said functional circuitry; and

a serial to parallel data packet converter interconnecting said parallel bus system and said external port and operable to read the packet identifier to determine the length of serial packets which are input through said port and to convert them into parallel data for supply in a forward direction to said bus system such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system,

said serial to parallel converter further comprising flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry,

wherein the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and wherein the parallel data causes the functional circuitry to execute an operation dependent on said information contained in the serial packets from which it has been converted.

2. A single chip integrated circuit device according to claim 1, wherein the data packet converter is further operable to convert parallel data into serial data packets and to allocate a packet type identifier to said serial packets indicating the type of message converted from parallel data from said bus system for use by external circuitry, in accordance with the information received from said bus system.

3. A single chip integrated circuit device according to claim 2, which comprises diagnostic control circuitry on-chip connected to said parallel bus system and operable to transmit diagnostic information onto said bus system for supply off-chip via said external port.

4. A single chip integrated circuit device according to claim 1, wherein the packet identifier of each serial packet includes a packet type identifier indicating the type of message, and wherein the data packet converter comprises message identification circuitry for determining from the packet identifier an indication of the type of message conveyed by the serial data packet and for implementing said message by supplying appropriate parallel data to said bus system.

5. A single chip integrated circuit device according to claim 4 wherein the bus system comprises a plurality of parallel buses and the data packet converter is operable to supply parallel data to a selected one of said parallel buses in dependence on the nature of the message identified by the packet identifier.

6. A single chip integrated circuit device according to claim 5, wherein the functional circuitry comprises memory interface circuitry for accessing memory local to the chip, and wherein at least one of said buses is a memory bus comprising address lines, data lines and control lines for allowing memory accesses to be implemented to said local memory from the external device.

7. A single chip integrated circuit device according to claim 5, wherein at least one of said buses in a register access bus for accessing on chip registers.

8. A single chip integrated circuit device according to claim 6, wherein when the message is a memory access request, the message includes an address to be accessed and the parallel data is supplied to one of said buses depending on said address.

9. A single chip integrated circuit device according to claim 7, wherein the on-chip registers include a control register for interrupting normal operation of the on-chip functional circuitry in dependence on parallel data loaded in the control register from said bus system.

10. A single chip integrated circuit device according to claim 1, wherein the functional circuitry comprises a processor.

11. A single chip integrated circuit device according to claim 1, wherein the functional circuitry comprises a plurality of processors.

12. A single chip integrated circuit device according to claim 1, in which the external device comprises an external debugging host, and said external port provides an external serial communication link for debugging commands from the external debugging host to the on-chip functional circuitry.

13. A single chip integrated circuit device according to claim 2, in which said external device is provided with a further memory which is local to the external device, and said external port provides a connection operable to allow said on-chip functional circuitry to access said further memory in addition to its local memory.

14. A single chip integrated circuit device according to claim 10, wherein said external port permits operating code to be supplied from said external device into said local memory for the processor, whereby the processor can be controlled by the external device to execute said operating code.

15. A single chip integrated circuit device comprising:

a bus system for effecting communication of parallel data on chip;

functional circuitry connected to said bus system for executing an operation in response to parallel data received from said bus system;

an external port comprising a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device, said serial data packets each including a packet identifier indicating the length of the data packet and information defining an operation to be executed by said functional circuitry; and

a serial to parallel data packet converter interconnecting said parallel bus system and said external port and operable to read the packet identifier to determine the length of serial packets which are input through said port and to convert them into parallel data for supply in a forward direction to said bus system such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system,

said serial to parallel converter further comprising flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry,

wherein the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and wherein the parallel data may cause some part of the functional circuitry to execute an operation dependent on said information contained in the serial packets from which it has been converted.

16. A method of effecting communication between a single chip integrated circuit device and an external device, the integrated circuit device comprising functional circuitry connected to an on-chip bus system for executing an operation in response to parallel data received from said bus system, the method comprising:

at the external device formulating serial data packets which each include a packet identifier indicating the length of the serial data packet and information defining an operation to be executed by said functional circuitry;

transmitting said serial data packets via a serial input connector of an external port of the single chip integrated circuit device;

reading the packet identifier to determine the length of serial packets supplied from said external device via the serial input connector and converting said serial data packets with a serial to parallel converter into parallel data for supply in a forward direction to said bus system such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus, without involving the functional circuitry;

wherein said serial to parallel converter further comprises flow control logic for indicating that it is ready to receive a subsequent serial data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry,

supplying said parallel data via the bus system to the functional circuitry to cause it to execute an operation dependent on said information contained in the serial packet.

17. A method according to claim 16, wherein parallel data supplied from the on-chip bus system is converted into serial packets for transmission off-chip via a serial output pin of the external port.

18. A method according to claim 16, wherein a packet identifier indicating the type of message converted from said parallel data is allocated to the serial packets in accordance with the information contained in said parallel data.