Single-chip microcomputer using adjustable timing to fetch data from an external memory

• US 6,125,431 A
• Filed: 06/09/1997
• Issued: 09/26/2000
• Est. Priority Date: 08/02/1996
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kobayashi, Jiro
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US08/871,537
• Time in Patent Office: 1,205 Days
• Field of Search: 395/568, 395/800.32, 395/842, 711/167, 711/2, 711/100, 711/154, 711/1, 712/32, 712/39, 712/43
• US Class Current: 711/154
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline

Abstract

It is an object of the present invention to provide a one-chip microcomputer which permits the access time for an external memory to be equal to that for an internal memory. The one-chip microcomputer 10 includes an internal ROM 11, control circuit 12, output terminals 13, input terminals 14, control circuit 15, selector 16, instruction register 17, delay circuit 18, and fetch control signal select gate 19. For selection of the external ROM 30, a control arrangement 20 and a delay circuit 18 are employed in one embodiment to adjust the time at which ROM data is fetched by the instruction register 17, based on the delay time for accessing the external ROM 30.

Claims

1. A single-chip microcomputer having input terminals and output terminals, in combination with an external ROM having input terminals that are connected to the output terminals of the single-chip microcomputer and having output terminals that are connected to the input terminals of the single-chip microcomputer,

wherein the external ROM stores instruction data;

and

wherein the single-chip microcomputer comprises;

an internal ROM which stores instruction data;

an internal/external switching signal generation circuit for generating an internal/external switching signal having a first digital level or a second digital level;

means for reading instruction data out of the internal and external ROMs;

a selector to select either instruction data that has been read out of the internal ROM or instruction data that has been read out of the external ROM according to the level of the internal/external switching signal;

an instruction register to receive the instruction data selected by the selector, the selected instruction data being fetched into the instruction register by a fetch control signal; and

means for emitting the fetch control signal to the instruction register at a timing which depends on the level of the internal/external switching signal, the means for emitting comprising a data fetch signal generation circuit which generates a data fetch signal, means connected to one of the output terminals of the single-chip microcomputer for generating a further signal, and means responsive to the internal/external switching signal for passing either the data fetch signal or the further signal to the instruction register as the fetch control signal.

2. The combination of claim 1, wherein the means responsive to the internal/external switching signal comprises a plurality of gates.

3. A single-chip microcomputer which is selectively connectable to an external storage means for outputting data, said single-chip microcomputer comprising:

an output terminal, the output terminal being selectively connectable to the external storage means;

an internal storage means for outputting data;

an internal/external switching signal generation circuit for generating an internal/external switching signal having a first digital level or a second digital level;

a selector to select either data that has been output by the internal storage means or data that has been output by the external storage means according to the level of the internal/external switching signal; and

means for emitting a fetch control signal for fetching the selected data from the selector at a timing which depends on the level of the internal/external switching signal, the means for emitting comprising a data fetch signal generation circuit which generates a data fetch signal, means connected to the output terminal for generating a further signal, and means responsive to the internal/external switching signal for selecting either the data fetch signal or the further signal for use as the fetch control signal.

4. The single-chip microcomputer of claim 3, wherein the means responsive to the internal/external switching signal comprises a plurality of gates.

5. A single-chip microcomputer which is selectively connectable to an external storage means for outputting data, said single-chip microcomputer comprising:

an output terminal, the output terminal being selectively connectable to the external storage means;

an internal storage means for outputting data;

an internal/external switching signal generation circuit for generating an internal/external switching signal having a first digital level or a second digital level;

a selector to select either data that has been output by the internal storage means or data that has been output by the external storage means according to the level of the internal/external switching signal;

an instruction register to receive the data selected by the selector, the selected data being latched into the instruction register by a fetch control signal;

means for emitting the fetch control signal to the instruction register at a timing which depends on the level of the internal/external signal, the means for emitting comprising a data fetch signal generation circuit which generates a data fetch signal, means connected to the output terminal for generating a further signal, and means responsive to the internal/external switching signal for passing either the data fetch signal or the further signal to the instruction register as the fetch control signal.

6. The single-chip microcomputer of claim 5, wherein the means responsive to the internal/external switching signal comprises a plurality of gates.

7. A single-chip microcomputer which is capable of executing first instructions and executing second instructions that are stored in an external storage unit that is connectable to the single-chip microcomputer, comprising:

an internal storage unit for storing the first instructions;

a program counter;

a first generation circuit for emitting a strobe signal;

first means for conveying the strobe signal and an address emitted by the program counter to the internal storage unit and to the external storage unit, the address and the strobe signal reaching the internal storage unit and then reaching the external storage unit after a delay;

an instruction register;

second means for selecting either a first instruction read out of the internal storage unit or a second instruction read out of the external storage unit in response to the address and the strobe signal, and for conveying the selected instruction to the instruction register;

a second generation circuit for emitting a fetch signal after the address and the strobe signal have been emitted; and

third means for conveying the fetch signal to the instruction register so that the instruction register latches the selected instruction into the instruction register a first period of time after the fetch signal was emitted, if the selected instruction is a first instruction, and so that the instruction register latches the selected instruction into the instruction register a second period of time after the fetch signal was emitted, if the selected instruction is a second instruction, the second period of time being longer than the first period of time to compensate for the delay.

8. The single-chip microcomputer of claim 7, wherein the internal storage unit and the external storage unit are read only memories.

9. The single-chip microcomputer of claim 7, further comprising a first set of terminals and a second set of terminals, the external storage unit being connectable to the first and second sets of terminals.

10. The single-chip microcomputer of claim 9, wherein the first means comprises conductors connecting the program counter and the first generation circuit to the internal storage unit, and a memory control circuit connected between the conductors and the terminals of the first set.

11. The single-chip microcomputer of claim 10, wherein the second means comprises a control circuit, a third generation circuit for generating an internal/external switching signal, a selector that is connected to the third generation circuit to receive the internal/external switching signal, the selector having a first input port that receives the first instructions from the internal storage unit, a second input port that receives the second instructions from the external storage unit by way of the second set of terminals and the control circuit, and an outlet port that emits the selected instructions to the instruction register.

12. The single-chip microcomputer of claim 11, wherein the third means comprises a delay circuit that is connected to the second generation circuit to delay the fetch signal, and a control circuit having a plurality of gates, the gates receiving input signals which include the fetch signal, the delayed fetch signal, and the internal/external switching signal, the gates of the control circuit generating an output which is supplied to the instruction register.

13. The single-chip microcomputer of claim 11, wherein the external memory unit has a chip-enable terminal, one of the terminals of the first set being connectable to the chip-enable terminal to convey the strobe signal to the chip-enable terminal, and wherein the third means comprises a control circuit having a plurality of gates, the gates having inputs that receive the fetch signal, the internal/external switching signal, and the strobe signal, the input that receives the strobe signal being connected to said one of the terminals of the first set.