Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions

• US 6,127,232 A
• Filed: 06/24/1999
• Issued: 10/03/2000
• Est. Priority Date: 12/30/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chatterjee, Amitava, Chapman, Richard A., Murtaza, Syed Suhail
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/339,528
• Time in Patent Office: 467 Days
• Field of Search: 438/291, 438/300, 438/305, 438/926, 438/301, 438/303, 438/592
• US Class Current: 438/291
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

Claims

1. A method of forming a MOS transistor structure comprising the acts of:

supplying a silicon substrate;

positioning a first layer of doped epitaxial silicon on the silicon substrate;

positioning a layer of gate oxide on the doped epitaxial silicon layer;

forming a disposable gate on the gate oxide, the disposable gate having sidewalls;

forming sidewall spacers on the disposable gate extending outwardly over the gate oxide;

removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate;

forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon;

forming an interlayer dielectric over the second layer of epitaxial silicon and the gate;

removing the dielectric from above the gate;

removing the disposable gate to form a recess;

removing the gate oxide layer to expose the first layer of doped epitaxial silicon, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess; and

depositing a permanent gate material in the recess and extending into the opposing laterally extended notches.

2. A method of forming a MOS transistor structure comprising the acts of:

supplying a silicon substrate;

positioning a first layer of doped epitaxial silicon on the silicon substrate;

positioning a layer of gate oxide on the doped epitaxial silicon layer;

forming a disposable gate on the gate oxide, the disposable gate having sidewalls;

forming sidewall spacers on the disposable gate extending outwardly over the gate oxide;

removing the gate oxide from the epitaxial silicon layer except underneath the disposable gate;

forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon;

forming an interlayer dielectric over the second layer of epitaxial silicon and the gate;

removing the dielectric from above the gate;

removing the disposable gate to form a recess;

removing the gate oxide layer to expose the first epitaxial silicon substrate;

forming an oxide with the first epitaxial silicon substrate layer, the oxide extending downwardly into the first epitaxial silicon substrate layer;

removing the oxide to define a groove in the first epitaxial silicon substrate layer, and undercut the sidewall spacers to form opposing laterally extending notch portions of the recess;

forming a gate oxide in the recess on the exposed first epitaxial silicon substrate layer; and

depositing a permanent gate material in the recess extending into the opposing laterally extended notches.

3. A method of forming a MOS transistor structure comprising the acts of:

supplying a silicon substrate;

positioning a first layer of doped epitaxial silicon on the silicon substrate;

positioning a layer of pad oxide on the doped epitaxial silicon layer;

forming a disposable gate on the pad oxide, the disposable gate having sidewalls;

forming sidewall spacers on the disposable gate extending outwardly over the pad oxide;

removing the pad oxide from the first epitaxial silicon layer except underneath the disposable gate;

forming a raised second layer of epitaxial silicon on the first layer of epitaxial silicon;

forming an interlayer dielectric over the second layer of epitaxial silicon and the gate;

removing the dielectric from above the gate;

removing the disposable gate to form a recess;

removing the pad oxide layer to expose the first epitaxial silicon substrate and to expose portions of the second layer of epitaxial silicon;

forming a gate oxide on the first epitaxial silicon substrate and exposed portions of the second layer of epitaxial silicon; and

depositing a permanent gate material in the recess and in the second layer of epitaxial silicon.