Method for forming a semiconductor device

• US 6,127,258 A
• Filed: 06/25/1998
• Issued: 10/03/2000
• Est. Priority Date: 06/25/1998
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Watanabe, Joy Kimi, Herrick, Matthew Thomas, Sparks, Terry Grant, Cave, Nigel Graeme
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US09/104,849
• Time in Patent Office: 831 Days
• Field of Search: 438/622, 438/623, 438/624, 438/625, 438/626, 438/627, 438/628, 438/629, 438/637-645, 438/598, 438/634, 438/636, 438/618, 438/692, 438/694, 438/703, 438/785
• US Class Current: 438/625
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric

Abstract

In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

Claims

1. A method for forming a semiconductor device, comprising:

forming via-level dielectric film overlying a semiconductor device substrate;

forming a trench-level dielectric film directly on and in contact with the via-level dielectric film;

etching a via opening in the trench-level dielectric film with a first etch chemistry, wherein the first etch chemistry has a higher etch selectivity to the trench-level dielectric film than to the via-level dielectric film;

providing a photoresist layer overlying the trench-level dielectric film, the photoresist layer having a photoresist opening overlying the via opening in the trench-level dielectric film;

etching the via-level dielectric film with a second etch chemistry to extend the via opening into the via-level dielectric film; and

etching into the trench-level dielectric film through the photoresist opening to form a trench opening.

2. The method of claim 1, wherein etching the trench-level dielectric film is carried out with the first etch chemistry.

3. The method of claim 1, wherein the steps are carried out sequentially, in the order of description.

4. The method of claim 1, wherein the via-level dielectric film comprises an inorganic material.

5. The method of claim 4, wherein the inorganic material comprises an oxide of silicon.

6. The method of claim 5, wherein the inorganic material comprises fluorinated silicon dioxide, formed by reacting TEOS gas with a fluorine-containing gas.

7. The method of claim 1, wherein the trench-level dielectric film comprises a low k material, said low k material having a dielectric constant not greater than approximately 3.5.

8. The method of claim 7, wherein the low k material comprises a material from a group consisting of organics, inorganics, and organic-inorganic hybrids.

9. The method of claim 8, wherein the low k material comprises an inorganic material, the inorganic material comprising a material from a group consisting of porous oxides, silsesquioxanes, and polysiloxanes.

10. The method of claim 1, further comprising forming a hardmask on the trench-level dielectric film, prior to etching the via opening into the trench-level dielectric film.

11. The method of claim 1, further comprising:

simultaneously filling the trench opening and the via

opening with a conductive material; and

forming a dual inlaid interconnect.

12. The method of claim 11, wherein the dual inlaid interconnect overlies and contacts with a first layer of metallization.

13. The method of claim 11, wherein the semiconductor device substrate has an active device including an active region, wherein the dual inlaid interconnect overlies and contacts said active region.

14. The method of claim 11, wherein the conductive material is selected from a group consisting of copper, aluminum, silver, and tungsten.

15. The method of claim 14, wherein the conductive material comprises copper.

16. The method of claim 1, further comprising depositing a protective layer in the via opening in the trench-level dielectric film, prior to providing the photoresist.

17. The method of claim 16, wherein the protective layer comprises a silicon-containing inorganic material.

18. The method of claim 1, wherein the first etch chemistry comprises oxygen, and the second etch chemistry comprises fluorine.

19. A method for forming a semiconductor device, comprising the sequential steps of:

forming via-level dielectric film overlying a semiconductor device substrate, said via-level dielectric film comprising an oxide of silicon;

forming a trench-level dielectric film directly on and in contact with the via-level dielectric film, said trench-level dielectric film comprising a low k dielectric material, said low k dielectric material having a dielectric constant not greater than 3.5;

etching a via opening in the trench-level dielectric film with a first etch chemistry, wherein the first etch chemistry has a higher selectivity to the trench-level dielectric film than to the via-level dielectric film;

providing a photoresist layer overlying the trench-level dielectric film, the photoresist layer having a photoresist opening over the via opening in the trench-level dielectric film;

etching the via-level dielectric film with a second etch chemistry to extend the via opening into the via-level dielectric film; and

etching into the trench-level dielectric film through the photoresist opening to form a trench opening.

20. The method of claim 19 further comprising:

simultaneously filling the trench opening and the via opening with a conductive material; and

removing portions of the conductive material, thereby forming a dual inlaid interconnect.