Method for fabricating MOSFET having increased effective gate length

• US 6,127,699 A
• Filed: 08/10/1999
• Issued: 10/03/2000
• Est. Priority Date: 06/10/1998
• Status: Expired due to Term

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chu, Chih-Hsun, Ni, Cheng-Tsung
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/371,378
• Time in Patent Office: 420 Days
• Field of Search: 438/270, 438/297, 438/303, 257/302, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334, 257/396, 257/397, 257/647, 257/900
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.

Claims

1. A semiconductor device, having a source, a drain and a gate electrode, fabricated by a process comprising the steps of:

forming a plurality of field oxide regions on said substrate to isolate a plurality of active areas;

forming a lightly doped region at one of said active areas;

forming a doped silicon layer including dopants on said lightly doped region at said one active area and on the field oxide regions isolating said one active area;

forming a patterned first dielectric layer on said doped silicon layer to define a gate area;

forming a second dielectric layer on said first dielectric layer and said doped silicon layer;

forming a third dielectric layer on said second dielectric layer;

anisotropically etching said third and second dielectric layers to form a plurality of spacer regions surrounding said gate area and to expose said doped silicon layer at said gate area;

forming a groove at said gate area by etching said exposed doped silicon layer and said substrate;

forming a gate oxide layer in said groove and forming said source and said drain in said substrate by substantially driving said dopants in said doped silicon layer into said substrate; and

forming said gate electrode in said groove.

2. The semiconductor device of claim 1, wherein said process further comprises the step of implanting second dopants into the exposed surface regions at said one active area between said steps of groove formation and gate oxide formation.

3. The semiconductor device of claim 1, wherein said doped silicon layer is a doped polysilicon layer.

4. The semiconductor device of claim 1, wherein said doped silicon layer is a doped amorphous silicon layer.

5. The semiconductor device of claim 3, wherein said doped silicon layer including dopants is formed by deposition of a polysilicon precursor in-situ-doped with said dopants.

6. The semiconductor device of claim 3, wherein said doped silicon layer including dopants is formed by sequentially depositing a polysilicon layer and implanting said dopants into said polysilicon layer.

7. The semiconductor device of claim 1, wherein said semiconductor device is a MOSFET.