Semiconductor device having an SOI structure and manufacturing method therefor

• US 6,127,702 A
• Filed: 09/16/1997
• Issued: 10/03/2000
• Est. Priority Date: 09/18/1996
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fukunaga, Takeshi, Ohtani, Hisashi, Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/931,697
• Time in Patent Office: 1,113 Days
• Field of Search: 438/289, 257/347, 257/353, 257/345
• US Class Current: 257/347
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.

Claims

1. An insulated-gate semiconductor device having an SOI structure, said device comprising:

a source region, a drain region and a channel forming region which are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer; and

a gate insulating film and a gate electrode formed on the channel forming region,

said channel forming region comprising;

carrier moving regions; and

impurity regions formed artificially and locally for pinning of a depletion layer developing from the drain region toward the channel forming region and the source region, said impurity regions containing an impurity element for shifting an energy band in such a direction that movement of electrons is obstructed.

5. An insulated-gate semiconductor device according to any one of claims 1 and 3 wherein said impurity element is for forming a built-in potential difference locally in the channel forming region.

6. An insulated-gate semiconductor device according to claim 1 or 3 wherein said impurity element belongs to group 13.

7. An insulated-gate semiconductor device according to claim 6 wherein said impurity element is boron.

10. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein said carrier moving regions are intrinsic or substantially intrinsic.

11. An insulated-gate semiconductor device according to claim 10 wherein said substantially intrinsic regions mean regions in which in the vicinity of a surface of the crystalline semiconductor a concentration of an impurity element for imparting one type of conductivity to the crystalline semiconductor is less than 5×

10¹⁵ atoms/cm³ and an oxygen concentration is less than 2×

10¹⁸ atoms/cm³.

12. An insulated-gate semiconductor device according to claim 10 wherein said substantially intrinsic regions mean regions in which in the vicinity of a surface of the crystalline semiconductor a concentration of an impurity element for imparting one type of conductivity to the crystalline semiconductor is less than 5×

10¹⁵ atoms/cm³ and an oxygen concentration is less than 1×

10¹⁷ atoms/cm³.

13. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein a width W of the channel forming region, a total width W_pi of the impurity regions, and a total width W_pa of regions between the impurity regions satisfy relationships W_pi /W=0.1 to 0.9, W_pa /W=0.1 to 0.9, and W_pi /W_pa =1/9 to 9.

14. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein in at least one cross-section taken by cutting the channel forming region in a direction perpendicular to a channel direction, the channel forming region is substantially regarded as a collection of a plurality of channel forming regions sectioned by the impurity regions.

15. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein a reduction in threshold voltage caused by a short channel effect occurring in the channel forming region during driving is compensated by an increase in threshold voltage caused by a narrow channel effect obtained by utilizing the impurity regions.

16. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein the impurity regions serve as regions for buffering stress that occurs in the crystalline semiconductor.

17. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein a total width of the carrier moving regions is within a range of 30 to 3,000 Å

.

18. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein said impurity regions have dot patterns.

19. An insulated-gate semiconductor device according to any one of claims 1 to 4 wherein said impurity regions have linear patterns substantially parallel with a channel direction.

21. The device of any one of claims 1 through 4 in combination with at least an electric apparatus selected from the group consisting of a liquid crystal display device, an EL display device, a CL display device, a TV camera, a personal computer, a car navigation apparatus, a TV projection apparatus, a video camera, and a portable information terminal apparatus including a cellular telephone and a mobile computer.

22. A device according to any one of claims 1 and 3 wherein said impurity element in said impurity regions is at a concentration of 1×

10¹⁷ to 1×

10²⁰ atoms/cm³.

2. An insulated-gate semiconductor device having an SOI structure, said device comprising:

a single crystal semiconductor substrate;

an insulating layer in the single crystal substrate;

a crystalline semiconductor on the insulating layer;

a source region, a drain region, and a channel forming region being formed in the crystalline semiconductor, each of the source and drain regions including a first impurity; and

a gate insulating film and a gate electrode being formed on the channel forming region,

said channel forming region comprising;

a plurality of carrier moving regions; and

a plurality of impurity regions being formed artificially and locally for pinning of a depletion layer developing from the drain region toward the channel forming region and the source region, said impurity regions including a second impurity for shifting an energy band in such a direction that movement of holes is obstructed,

wherein the second impurity has an opposite conductivity to the first impurity.

8. An insulated-gate semiconductor device according to claim 2 or 4 wherein said second impurity belongs to group 15.

9. An insulated-gate semiconductor device according to claim 8 wherein said second impurity is phosphorus or arsenic.

23. A device according to any of claims 2 and 4, wherein the second impurity is for forming a built-in potential difference locally in the channel forming region.

24. A device according to any one of claims 2 and 4, wherein the second impurity in the impurity regions is at a concentration of 1×

10¹⁷ to 1×

10²⁰ atoms/cm³.

3. An insulated-gate semiconductor device having an SOI structure, said device comprising:

a source region, a drain region and a channel forming region which are formed by using a crystalline semiconductor formed on an insulative substrate or an insulating layer; and

a gate insulating film and a gate electrode formed on the channel forming region,

said channel forming region comprising;

carrier moving regions; and

impurity regions formed artificially and locally by adding an impurity element to control a threshold voltage to a given value, said impurity element shifting an energy band in such a direction that movement of electrons is obstructed.

20. An insulated-gate semiconductor device according to claim 3 or 4 wherein said threshold voltage is controlled by controlling widths of the carrier moving regions.

4. An insulated-gate semiconductor device having an SOI structure, said device comprising:

a single crystal semiconductor substrate;

an insulating layer in the single crystal substrate;

a crystalline semiconductor on the insulating layer;

a source region, a drain region and a channel forming region being formed in the crystalline semiconductor, each of the source and drain regions including a first impurity; and

a gate insulating film and a gate electrode being formed on the channel forming region,

said channel forming region comprising;

a plurality of carrier moving regions; and

a plurality of impurity regions being formed artificially and locally by adding a second impurity to control a threshold voltage to a given value, said second impurity shifting an energy band in such a direction that movement of holes is obstructed,

wherein the second impurity has an opposite conductivity to the first impurity.

25. An insulating gate semiconductor device having an SOI structure, said device comprising:

a single crystal semiconductor substrate;

an insulating layer in the single crystal substrate;

a single crystal semiconductor layer on the insulating layer;

a source region, a drain region, and a channel forming region being formed in the single crystal semiconductor layer, each of the source and drain regions including a first impurity; and

a gate electrode being formed over the channel forming region with a gate insulating film therebetween,

said channel forming region comprising;

a plurality of carrier moving regions; and

a plurality of impurity regions each including a second impurity,

wherein the second impurity has an opposite conductivity to the first impurity.

26. A device according to claim 25, wherein the insulated gate semiconductor device is an n-type insulated gate field effect transistor,

wherein the first impurity is an n-type impurity while the second impurity is a p-type impurity.

27. A device according to claim 25, wherein the insulated gate semiconductor device is an n-type insulated gate field effect transistor,

wherein the first impurity comprises phosphorus while the second impurity comprises boron.

28. A device according to claim 25, wherein the insulated gate semiconductor device is a p-type insulated gate field effect transistor,

wherein the first impurity is a p-type impurity while the second impurity is an n-type impurity.

29. A device according to claim 25, wherein the insulated gate semiconductor device is a p-type insulated gate field effect transistor,

wherein the first impurity comprises boron while the second impurity comprises at least one selected from the group consisting of phosphorus and arsenic.

30. A device according to claim 25, wherein the second impurity in the plurality of impurity regions is at a concentration of 1×

10¹⁷ to 1×

10²⁰ atoms/cm³.

31. A device according to claim 25, wherein a width W of the channel forming region, a total width W_pi of the impurity regions, and a total width W_pa of regions between the plurality of impurity regions satisfy relationships W_pi /W=0.1 to 0.9, W_pa /W=0.1 to 0.9, and W_pi /W_pa =1/9 to 9.

32. A device according to claim 25, wherein a total width of the plurality of carrier moving regions is within a range of 30 to 3,000 Å

.

33. A device according to claim 25, wherein each of the plurality of impurity regions has a dot pattern.

34. A device according to claim 25, wherein each of the plurality of impurity regions has a linear pattern being parallel with a channel direction.

35. The device of claim 25 in combination with at least an electric apparatus selected from the group consisting of a liquid crystal display device, an EL display device, a CL display device, a TV camera, a personal computer, a car navigation apparatus, a TV projection apparatus, a video camera, and a portable information terminal apparatus including a cellular telephone and a mobile computer.