Test carrier for attaching a semiconductor device

• US 6,127,833 A
• Filed: 01/04/1999
• Issued: 10/03/2000
• Est. Priority Date: 01/04/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wen-Teng, Hsieh, Chi-Min, Chiu, Chwei-Ching
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US09/225,382
• Time in Patent Office: 638 Days
• Field of Search: 324/755, 324/754, 324/765
• US Class Current: 324/756.02
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors

Abstract

A method for forming a semiconductor test carrier including an insulating substrate having a top surface, a bottom surface, periphery; with a rectangular cavity centrally located on the top surface and extending through to the bottom surface. A conductive ground trace formed on the top surface at the periphery of the cavity with conductive corner power traces formed adjacent each corner of the ground trace, with a ruled pattern of conductive wire bond pads encircling the corner power traces. Wire bond pads are formed in a linear array on each of the four sides encircling the power traces. A first interstitial ball pad array encircles the conductive wire bond pads and connects with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface. A glass plate is attached to the underside of the insulated substrate to form a bottom supporting surface in the rectangular cavity. A semiconductor device is placed in the cavity and its backside adhesively bonded to the glass plate. The appropriate input/output terminals of the device are connected to appropriate wire bond pads and traces on the top surface of the substrate with metallurgically bonded conductive wire. The exposed ends of the wires are encapsulated with a sealing polymer.

Claims

1. A semiconductor device test carrier comprising:

a printed circuit board (CB) substrate having a top surface, a bottom surface, and periphery;

a rectangular cavity centrally located on said top surface and extending through to said bottom surface;

said cavity is concentric within a conductive ground trace patternly provided on the top surface of said PCB substrate;

conductive corner power traces are provided adjacent each corner of said ground trace, and

a ruled pattern of conductive wire bond fingers encircling said corner power traces are also provided in a linear array on each of four sides encircling said power traces;

a first interstitial ball pad array encircling said conductive wire bond pads connects the bottom surface by way of conductive vias and communicates with a second interstitial ball pad array at the bottom surface;

a glass plate fitted and bonded to the underside of said PCB substrate forms a transparent bottom supporting surface for said rectangular cavity;

a semiconductor device with its backside bonded to said glass substrate within said cavity, bares both front and back sides of said device for EMMI failure analysis.

2. The device test carrier described in claim 1 further comprising:

said semiconductor device having a plurality of bonding pads on its front side which serve as input/output terminals for said device;

wires connected said bonding pads of said device to appropriate wire bond fingers and traces of said substrate , said connected wires encapsulated between said device and said device test carrier.

3. The device test carrier described in claim 1 wherein the material comprising said insulating substrate in taken from the group consisting of epoxy-glass based and phenolic based materials.

4. The device test carrier described in claim 2 wherein the material comprising said insulating substrate in taken from the group consisting of epoxy-glass based and phenolic based materials.

5. The device test carrier described in claim 1 wherein said ball pads are generally spherical shaped members configured for multiple electrical engagements with mating electrical connectors of a test apparatus.

6. The device test carrier described in claim 1 wherein the material comprising the ball pads is copper and plated with gold.

7. The device test carrier described in claim 2 wherein the material comprising the ball pads is copper plated with gold.

8. The device test carrier described in claim 2 wherein the outside dimensions of the glass plate are greater than the periphery dimensions of the cavity to permit bonding to the bottom surface of the insulating substrate.

9. The device test carrier described in claim 2 wherein the bonding material used for bonding the device die to the glass plate and the glass plate to the bottom of the insulating substrate is taken from the group of thermally conductive die adhesives consisting of resin type epoxy or polyimide with an oxide filler for enhancing heat transfer.

10. The device test carrier described in claim 2 wherein the encapsulating material used for sealing the wire connections is taken from the group of polymeric materials consisting of silicone elastomers, ultrasoft silicone gels, low-stress epoxies, low thermal-expansion coefficient and photodefinable polyimides and cyclobutenes.

11. The device test carrier described in claim 2 wherein functional testing of said semiconductor device is performed after encapsulation.

12. The device test carrier described in claim 1 wherein said first interstitial ball pad array situated on the top surface interconnects with said second interstitial ball pad array situated on the bottom surface thereby permitting power pluggability to an analysis test socket from either the top or bottom ball pad arrays.

13. The device test carrier described in claim 12 wherein reversible pluggability with an analysis test socket allows thermal sensing of both surfaces of said semiconductor device during failure analysis.

14. A method for forming a semiconductor device test carrier using a printed circuit board (PCB) comprising the steps of providing an off-the-shelf PCB to be modified to receive a semiconductor device, said PCB having a top surface, a bottom surface and periphery;

machining a rectangular cavity centrally located on the top surface and extending through to the bottom surface, said rectangular cavity is positioned concentric and within a conductive ground trace patternly formed on the top surface of said PCB, with conductive corner power traces patternly formed adjacent each corner of said ground trace, and

providing a ruling pattern of conductive wire bond pads encircling the corner power traces, said wire bond pads formed in a linear array on each of four sides encircling the power trace, and

providing a first interstitial ball pad array encircling the conductive wire bond pads for connecting with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface, whereas each of said conductive wire bond fingers comprising said ruling pattern have conductive traces connected to said first pattern of ball pads to establish electrical communication between said conductive wire bond fingers and said first pattern of ball pads;

providing and attaching a glass plate, with an adhesive, to the underside of the insulated substrate to form a transparent bottom supporting surface for the rectangular cavity;

providing a semiconductor device having a front side, a back side and periphery;

placing said device into cavity of said substrate and adhesively bonding its backside to the glass plate thereby baring both backside and frontside for EMMI failure analysis, said device showing a plurality of bonding pads on its front side which serve as input/output terminals for said device;

providing conductive wire and wire bonder for connecting said bonding pads of said device to appropriate wire bond fingers and traces of said substrate; and

providing an encapsulate for encapsulating all wire connections between said device and said device test carrier.

15. The method as described in claim 14 wherein the material comprising said insulating substrate in taken from the group consisting of epoxy-glass based and phenolic based materials.

16. The method as described in claim 14 wherein the material comprising said insulating substrate in taken from the group consisting of epoxy-glass based and phenolic based materials.

17. The method as described in claim 14 wherein said ball pads are generally spherical shaped members configured for multiple electrical engagements with mating electrical connectors of a test apparatus.

18. The method as described in claim 14 wherein the material comprising the ball pads is copper plated with gold.

19. The method as described in claim 14 wherein the material comprising the ball pads is copper plated with gold.

20. The method as described in claim 14 wherein the outside dimensions of the glass plate are greater than the periphery dimensions of the cavity to permit bonding to the bottom surface of the insulating substrate.

21. The method as described in claim 14 wherein the bonding material used for bonding the device die to the glass plate and the glass plate to the bottom of the insulating substrate is taken from the group of thermally conductive die adhesives consisting of resin type epoxy or polyimide with an oxide filler for enhancing heat transfer.

22. The method as described in claim 14 wherein the encapsulating material used for sealing the wire connections is taken from the group of polymeric materials consisting of silicone elastomers, ultrasoft silicone gels, low-stress epoxies, low thermal-expansion coefficient and photodefinable polyimides and cyclobutenes.

23. The method as described in claim 14 wherein functional testing of said semiconductor device is performed after encapsulation.

24. The method as described in claim 14 wherein said first interstitial ball pad array situated on the top surface interconnects with said second interstitial ball pad array situated on the bottom surface thereby permitting power pluggability to an analysis test socket from either the top or bottom ball pad arrays.

25. The method as described in claim 24 wherein power pluggability to an analysis test socket allows visual access for thermal sensing for both the top and bottom surfaces of said semiconductor device during failure analysis.