Three dimensional mounting assembly for integrated circuits

• US 6,128,201 A
• Filed: 05/22/1998
• Issued: 10/03/2000
• Est. Priority Date: 05/23/1997
• Status: Expired due to Fees

• Current Assignee: Technology IP Holdings Incorporated
• Original Assignee: Alpine Microsystems, Inc.
• Inventors: Brown, Sammy K., Avery, George E., Wiggin, Andrew K., Beal, Sam, Todd, Tom L.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/083,626
• Time in Patent Office: 865 Days
• Field of Search: 257/723, 257/724, 257/678, 257/700, 361/784, 361/758, 361/728, 361/729, 361/730, 361/733, 361/735, 361/736, 361/788, 361/790, 361/803, 361/807, 361/809, 365/51, 365/52, 365/63, 439/59, 439/61, 439/65, 439/82, 439/83
• US Class Current: 361/784
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 1/182 associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 3/3442 having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/423 characterised by electroplating method
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

A system and method for efficiently interconnecting a plurality of ICs, thereby improving the electrical performance of the overall system. In one embodiment of the system of the present invention, a plurality of carriers corresponds to a plurality of ICs, and a board has a plurality of board regions for receiving the plurality of ICs and are arranged so as to be attached to a backplane forming a vertical stack of boards.

Claims

1. A mounting assembly for an integrated circuit comprising:

a first insulative member having a plurality of bond sites disposed thereon and a plurality of signal traces, each of which extends from one of said plurality of bond sites, with a subgroup of said plurality of bond sites lying on a surface of said first insulative member extending in a first plane;

a second insulative member having a plurality of signal paths and a plurality of bond pads disposed thereon, with a subset of said plurality of bond pads lying on a face of said second insulative member extending in a second plane, with said first plane extending transversely to said second plane and said first insulative member having a plurality of apertures formed therein, said second insulative member including a plurality of tenons having a shape complementary to a cross-section of said apertures and being disposed therein, defining a joint between said first and second insulative members; and

a brace, coupled to said second insulative member, to reduce movement about said joint.

2. The mounting assembly as recited in claim 1 wherein said brace includes having one of said plurality of tenons include a first section extending from said face transversely to said second plane and terminating in a second section extending parallel to said second plane and transversely to said first plane.

3. The mounting assembly as recited in claim 1 further including a plurality of said second insulative members.

4. The mounting assembly as recited in claim 1 wherein said second insulative member includes a periphery and further including a plurality of said first insulative members, each of which lies in a differing plane, with said brace including a first subset of said plurality of tenons disposed in apertures of one of said plurality of insulative members, with a second subset of said plurality of tenons being disposed in the apertures of a differing first insulative member of said plurality of first insulative members.

5. The mounting assembly as recited in claim 1 further including a stud extending from said face, with said stud being positioned proximate to an edge of said face disposed opposite to said first insulative member.

6. The mounting assembly as recited in claim 1 wherein said first and second insulative member are formed from silicon.

7. The mounting assembly as recited in claim 1 wherein a first group of said plurality of bond pads enclose a region of said first insulative member and a second group of said plurality of signal paths are associated with said first group of bond pads and extend away from said region, defining an electrically nonconductive area, and further including a routing carrier having a plurality of conductive traces and a plurality of conductive bond areas, a third group of which superimposes said first group bond pads so that each of said third group bond areas superimposes one of said first group of bond pads, with one of said plurality of conductive traces superimposing said nonconductive area and extending between a pair of bond areas of said third group so as to place a pair of said bond pads of said first group in electrical communication.

8. The substrate as recited in claim 7 wherein said integrated circuit is coupled to the remaining bond areas of said routing carrier and is positioned thereon so as to superimpose said nonconductive area.

9. The substrate as recited in claim 7 wherein said integrated circuit is coupled to the remaining bond pads of said routing carrier and said nonconductive area includes an orifice having an area which exceeds a cross-sectional area of said integrated circuit, said integrated circuit being positioned on said routing carrier so as to fit within said orifice.

10. A mounting assembly for an integrated circuit comprising:

a first insulative member having a plurality of bond sites disposed thereon and a plurality of signal traces, each of which extends from one of said plurality of bond sites, with a subgroup of said plurality of bond sites lying on a surface of said first insulative member extending in a first plane;

a plurality of second insulative members, each of which includes a face having a plurality of signal paths and a plurality of bond pads disposed thereon, said face being surrounded by a periphery and extending in a second plane orientated transversely to said first plane, with a pair of tenons extending from said periphery, said first insulative member having a plurality of spaced-apart apertures formed therein, with each of said pair of tenons of each of said plurality of second insulative members being disposed within one of said plurality of spaced-apart apertures with each of said plurality of second insulative members extending from said first insulative member parallel to an adjacent second insulative member upon said plurality of second insulative members and said first insulative member reaching a final seating position, and a stud extending from said face, with said stud being positioned proximate to a portion of said periphery disposed opposite to said first insulative member.

11. The mounting assembly as recited in claim 10 further including a conductive fusible alloy rigidly affixing one of said bonds pads with one of said bond sites.

12. The mounting assembly as recited in claim 11 wherein said plurality of bond pads are arranged as a groups, each of which encloses a region of said second insulative member, forming multiple regions, with signal traces associated with each of said plurality of groups, extending away from said region, defining a plurality of electrically nonconductive areas, and further including a plurality of routing carriers each of which has a plurality of conductive traces and a plurality of conductive bond areas, a subportion of said conductive bond areas superimposes one of said groups of said plurality of bond pads so that each of said conductive bond areas of said subportion superimposes said one of said groups, with one of said plurality of conductive traces superimposing said nonconductive area and extending between a pair of bond areas of said subportion so as to place a pair of said bond pads of said one of said groups in electrical communication.

13. The mounting assembly as recited in claim 12 wherein an integrated circuit is coupled to the remaining bond areas of each of said routing carrier and is positioned thereon so as to superimpose said nonconductive area.

14. The mounting assembly as recited in claim 13 wherein said nonconductive area includes an orifice having an area which exceeds a cross-sectional area of said integrated circuit, said integrated circuit being positioned on said routing carrier so as to fit within said orifice.

15. The mounting assembly as recited in claim 14 wherein said first and insulative member and each of said plurality of second insulative members are formed from silicon.

16. A method of routing signal paths on first and second insulative members comprising steps of:

depositing, on said first insulative member, a plurality of spaced-apart bond sites and a plurality of signal traces, with each of said plurality of signal traces extending from one of said plurality of bond sites, and a distance between adjacent bond sites defining a first pitch, said first insulative member including a surface lying in a first plane with said plurality of bond sites and said plurality of signal traces lying in said first plane;

depositing, on said second insulative member, a plurality of spaced-apart bond pads and a plurality of signal paths, with each of said plurality of signal paths extending from one of said plurality of bond pads and a distance between adjacent bond pads defining a second pitch, said second insulative member including a face lying in a second plane with said plurality of bond pads and said plurality of signal paths lying in said second plane;

forming a plurality of spaced-apart apertures in said first insulative member, within a first predetermined tolerance;

forming a plurality of spaced-apart tenons in said second insulative member within a second predetermined tolerance, with each of said plurality of spaced-apart tenons being adapted to fit into one of said plurality of spaced-apart apertures;

coupling said first and second insulative members together defining a joint therebetween; and

bracing said second insulative member to reduce movement about said joint.

17. The method as recited in claim 16 wherein each of said plurality of bond pads are positioned adjacent to one of said plurality of bond sites after said coupling step and further including the step of soldering each of said plurality of bond sites to one of said plurality of bond pads positioned adjacent thereto.

18. The method as recited in claim 16 wherein said second insulative member includes a periphery with each of said plurality of tenons extending from said periphery with said first and second planes being positioned orthogonally to each other after said coupling step.

19. The method as recited in claim 16 wherein said first and second insulative members are formed from a silicon compound.