Hybrid memory device

• US 6,128,218 A
• Filed: 08/19/1999
• Issued: 10/03/2000
• Est. Priority Date: 10/28/1998
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: You, Min-Young, Park, Jong-Hoon
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/377,163
• Time in Patent Office: 411 Days
• Field of Search: 356/156, 356/154, 356/205, 356/207, 356/208
• US Class Current: 365/156
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Abstract

A hybrid memory device according to the present invention has a RAM cell and a ROM cell that separately operate, and is capable of loading data in the ROM cell to the RAM cell. In such a hybrid memory device, to transfer the data in the ROM cell to common bit lines, transistors are respectively provided between the bit lines and the ROM cell. Accordingly, even when loading the data in the ROM cell to the RAM cell, the RAM and ROM cells can be separately operated.

Claims

1. A memory device comprising

first and second bit lines;

a first memory cell coupled between the first and second bit lines and responsive to a first word line signal;

a second memory cell coupled between the first and second bit lines and responsive to a second word line signal, the first and second memory cells being different type of memory cells;

a first switching device coupled to at least one of the first and second bit lines to allow at least one of transfer of data to and from the first memory cell; and

a second switching device coupled to at least one of the first and second bit lines for transfer of data from the second memory cell.

2. The memory device of claim 1, wherein the first memory cell operates independently of the second memory cell.

3. The memory of device of claim 1, wherein the first memory cell and the second memory cell perform a read operation concurrently.

4. The memory of device of claim 1, wherein the first memory cell performs a write operation concurrently with the second memory cell performing a read operation.

5. The memory of device of claim 1, wherein the first memory cell performs a read operation while the second memory cell is disabled.

6. The memory of device of claim 1, wherein the first memory cell performs a write operation while the second memory cell is disabled.

7. The memory of device of claim 1, wherein the second memory cell performs a read operation while the first memory cell is disabled.

8. The memory of device of claim 1, wherein the first memory cell is a random access memory cell and the second memory cell is a read-only memory cell.

9. The memory device of claim 8, wherein the random access memory cell is a static random access memory cell.

10. The memory device of claim 9, wherein the read-only memory cell operates as one of NAND logic gates and NOR logic gates.

11. The memory of device of claim 1, wherein the first switching device comprises first and second transistors coupled between the first memory cell and the first and second bit lines, respectively.

12. The memory device of claim 11, wherein the first memory cell comprises first, second, third and fourth memory cell transistors, each transistor of the first memory cell and the first switching device having first and second electrodes and a control electrode wherein:

the first electrodes of each of the first and second memory cell transistors are coupled to each other in series, and commonly coupled to the control electrodes of the third and fourth memory cell transistors and the second electrode of the first transistor of the first switching device;

the first electrodes of each of the third and fourth memory cell transistors are coupled in series, and commonly coupled to the control electrodes of the first and second memory cell transistors and the second electrode of the second transistor of the first switching device;

the first electrodes of each of the first and second transistor of the first switching device are coupled to the first and second bit lines, respectively; and

the control electrodes of each of the first and second transistors of the first switching device are coupled for receiving the first word line signal.

13. The memory device of claim 1, wherein the second switching device comprises first and second transistors, each having first and second electrodes and a control electrode, wherein

the first electrode of the first transistor is coupled to the first bit line, the second electrode of the first transistor is coupled to the second memory cell, and the control electrode of the first transistor is coupled for receiving an activation signal;

and

the first electrode of the second transistor is coupled to the second bit line, the second electrode of the second transistor is coupled to the second memory cell, and the control electrode of the second transistor is coupled for receiving the activation signal.

14. The memory device of claim 13, wherein the second memory cell comprises:

first and second memory cell transistors, each having first and second electrodes and a control electrode, wherein the first electrode of the first memory cell transistor is coupled in series with the second electrode of the first transistor of the second switching device, the second electrode of the first memory cell transistor is coupled for receiving a prescribed first potential, and the control electrode of the first memory cell transistor is coupled for receiving the second word line signal; and

the first electrode of the second memory cell transistor is coupled in series with the second electrode of the second transistor of the second switching device, the second electrode of the second memory cell transistor is coupled for receiving the first prescribed potential, and the control electrode is coupled for receiving the second word line signal.

15. The memory device of claim 13, wherein the second switching device further comprises:

first and second transfer gates coupled to the first and second bit lines, respectively; and

the first transfer gate being responsive to first and second control signals and the second transfer gate being responsive to third and fourth control signals.

16. The memory device of claim 15, wherein the second memory cell comprises first, second, third and fourth memory cell transistors, each having first and second electrodes and a control electrode,

the first electrodes of the first and second memory cell transistors being coupled in series to the second electrodes of the first and second transistors, respectively, of the second switching device;

the second electrodes of each of the first and second memory cell transistors being coupled in series to the first electrodes of the third and fourth memory cell transistors, respectively;

the control electrodes of the first and second memory cell transistors being commonly coupled for receiving the second word line signal;

the control electrodes of the third and fourth memory cell transistors being commonly coupled for receiving to a third word line signal; and

the second electrodes of the third and fourth memory cell transistors being coupled to a prescribed first potential.

17. The memory device of claim 15, wherein the second control signal is an inverted signal of the first control signal, and the fourth control signal is an inverted signal of the third control signal.

18. The memory device of claim 15, wherein the first and third control signals are identical signals, and the second and fourth control signals are identical signals.

19. The memory device of claim 1, wherein the second memory cell operates as one of NAND logic gates and NOR logic gates.

20. The memory device of claim 1, wherein the second switching device includes:

first and second transfer gates coupled to the first and second bit lines, respectively; and

the first transfer gate being responsive to first and second control signals, and the second transfer gate being responsive to third and fourth control signals.

21. A memory device comprising:

first and second bit lines;

a random access memory cell coupled between the first and second bit lines and responsive to a first word line signal;

a read-only memory cell coupled between the first and second bit lines and responsive to a second word line signal;

a first switching device coupled to at least one of the first and second bit lines to allow at least one of transfer of data to and from the random access memory cell; and

a second switching device coupled to at least one of the first and second bit lines for transfer of data from the read-only memory cell.

22. The memory device of claim 21, wherein the random access memory cell performs one of:

(1) an operation independent of an operation of the read-only memory cell;

(2) a read operation concurrent with the read-only memory cell;

(3) a write operation concurrent while the read-only memory cell performs a read operation;

(4) a read operation while the read-only memory cell is disabled;

(5) a write operation while the read-only memory cell is disabled; and

(6) a disabling operation that disables the random-access memory cell while the read-only memory cell performs a read operation.

23. The memory device of claim 21, wherein the first switching device comprises first and second transistors coupled between the random access memory cell and the first and second bit lines, respectively.

24. The memory device of claim 23, wherein the random access memory cell comprises first, second, third and fourth memory cell transistors, each transistor of the random access memory cell and the first switching device having first and second electrodes and a control electrode, wherein:

the first electrodes of each the first and second memory cell transistors are coupled to each other in series, and commonly coupled to the control electrodes of the third and fourth memory cell transistors and the second electrode of the first transistor of the first switching device;

the first electrodes of each of the third and fourth memory cell transistors are coupled in series, and commonly coupled to the control electrodes of the first and second memory cell transistors and the second electrode of the second transistor of the first switching device;

the first electrodes of each of the first and second transistors of the first switching device are respectively coupled to the first and second bit lines; and

the control electrodes of each of the first and second transistors of the first switching device are coupled for receiving the first word line signal.

25. The memory device of claim 21, wherein the second switching device comprises first and second transistors, each having first and second electrodes and a control electrode, wherein:

the first electrode of the first transistor is coupled to the first bit line, the second electrode of the first transistor is coupled to the read-only memory cell, and the control electrode of the first transistor is coupled for receiving an activation signal; and

the first electrode of the second transistor is coupled to the second bit line, the second electrode of the second transistor is coupled to the read-only memory cell, and the control electrode of the second transistor is coupled for receiving the activation signal.

26. The memory device of claim 25, wherein the read-only memory cell comprises:

first and second memory cell transistors, each having first and second electrodes and a control electrode, wherein the first electrode of the first memory cell transistor is coupled in series with the second electrode of the first transistor of the second switching device, the second electrode of the first memory cell transistor is coupled for receiving a prescribed first potential, and the control electrode of the first memory cell transistor is coupled for receiving the second word line signal; and

the first electrode of the second memory cell transistor is coupled in series with the second electrode of the second transistor of the second switching device, the second electrode of the second memory cell transistor is coupled for receiving the first prescribed potential, and the control electrode is coupled for receiving the second word line signal.

27. The memory device of claim 21, wherein the second switching device includes:

first and second transfer gates coupled to the first and second bit lines, respectively; and

the first transfer gate being responsive to first and second control signals and the second transfer gate being responsive to third and fourth control signals.

28. The memory device of claim 27, wherein the read-only memory cell comprises first, second, third and fourth memory cell transistors, each having first and second electrodes and a control electrode,

the first electrodes of the first and second memory cell transistors being coupled in series to the second electrodes of the first and second transistors, respectively, of the second switching device;

the second electrodes of each of the first and second memory cell transistors being coupled in series to the first electrodes of the third and fourth memory cell transistors, respectively;

the control electrodes of the first and second memory cell transistors being commonly coupled for receiving the second word line signal;

the control electrodes of the third and fourth memory cell transistors being commonly coupled for receiving a third word line signal; and

the second electrodes of the third and fourth memory cell transistors being coupled to a prescribed first potential.

29. The memory device of claim 27, wherein the second control signal is an inverted signal of the first control signal, and the fourth control signal is an inverted signal of the third control signal.

30. The memory device of claim 27, wherein the first and third control signals are identical signals, and the second and fourth control signals are identical signals.

31. The memory device of claim 21, wherein the read-only memory cell operates as one of NAND logic gates and NOR logic gates, and the random access memory cell is a static random access memory cell.