Apparatus for enabling EEPROM functionality using a flash memory device

• US 6,128,220 A
• Filed: 01/21/1999
• Issued: 10/03/2000
• Est. Priority Date: 01/21/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Banyai, Chris J., Brown, Robert H.
• Primary Examiner(s): Dinh, Son T.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/235,064
• Time in Patent Office: 621 Days
• Field of Search: 365/185.05, 365/185.29, 365/185.35, 365/185.11, 365/230.03, 365/63
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors

Abstract

An apparatus for enabling EEPROM functionality using a flash memory device comprises a number of bytes of non-volatile memory. The flash memory device has per-byte source isolation and per-byte drain isolation of a number of non-volatile flash memory cell transistors. The flash memory device provides a byte-alterable non-volatile memory.

Claims

1. A memory device, comprising:

a memory array, the memory array including;

one or more blocks of memory cells, each memory cell within the one or more blocks includes a source and a drain, and

wherein each block of memory cells includes,

a source isolation device configured to isolate the source of each memory cell within the block from other blocks of memory cells, and

a drain isolation device configured to isolate the drain of each memory cell within the block from other blocks of memory cells.

2. The memory device of claim 1, wherein the source isolation device is configured to isolate the source of each memory cell within the block from a source of a memory cell within other blocks of memory cells.

3. The memory device of claim 1, wherein the drain isolation device is configured to isolate the drain of each memory cell within the block from a drain of a memory cell within other blocks of memory cells.

4. The memory device of claim 1, wherein each memory cell within the one or more blocks of memory includes a gate.

5. The memory device of claim 4, wherein each block of memory cells further includes:

a gate isolation device configured to isolate the gate of each memory cell within the block from other blocks of memory cells.

6. The memory device of claim 5, wherein the gate isolation device is configured to isolate the gate of each memory within the block from a gate of a memory cell within other blocks of memory cells.

7. The memory device of claim 1, wherein the one or more blocks of memory cells are block alterable.

8. The memory device of claim 1, wherein the one or more blocks of memory cells are non-volatile memory.

9. The memory device of claim 1, wherein the one or more blocks of memory cells are non-volatile memory for a flash memory device.