Method and apparatus for enhancing the performance of semiconductor memory devices

• US 6,128,237 A
• Filed: 12/06/1999
• Issued: 10/03/2000
• Est. Priority Date: 04/10/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Shirley, Brian
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/455,365
• Time in Patent Office: 302 Days
• Field of Search: 365/205, 365/207, 365/210, 365/230.06, 365/194
• US Class Current: 365/207
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.

Claims

1. A method of operating a memory circuit comprising the steps of:

activating a word line of the memory circuit by propagating a first signal along the word line, the first signal having a propagation time period associated with propagating the word line; and

sequentially activating a plurality of sense amplifiers connected to digit lines of the memory circuit within the propagation time period of the first signal.

2. The method of claim 1, wherein the sense amplifiers are sequentially activated in a direction from a first sense amplifier located closest to a front edge of the activated word line to a last sense amplifier located closest to a back edge of the activated word line.

5. The method of claim 1 further comprising the step of propagating a second signal along a dummy word line coupled to the memory circuit, the second signal tracking the propagation of the first signal, and wherein the sequential activation of the plurality of sense amplifiers is performed in accordance with the propagation of the second signal.

6. The method of claim 5, wherein a duration of said second signal is not longer than the propagation time period of the first signal.

3. The method of clam 1 further comprising the step of grouping the digit lines into blocks of digit lines, wherein each block comprises at least two digit lines.

4. The method of claim 3 further comprising the step of connecting each sense amplifier to a block of digit lines.

7. A method of operating a memory circuit comprising the step of:

sequentially activating a plurality of sense amplifiers connected to a plurality of digit lines of the memory circuit, wherein the sense amplifiers are activated within a time period defined by a propagation time of an activation signal propagating along an activated word line of the memory circuit.

8. The method of claim 7, wherein the sense amplifiers are sequentially activated in a direction from a first sense amplifier located closest to a front edge of the activated word line to a last sense amplifier located closest to a back edge of the activated word line.

9. The method of claim 7 further comprising the step of grouping the digit lines into blocks of digit lines, wherein each block comprises at least two digit lines.

10. The method of claim 9 further comprising the step of connecting each sense amplifier to a block of digit lines.

11. The method of claim 7, wherein said sequentially activating step comprises:

generating a tracking signal propagating along a dummy word line coupled to the memory circuit, the tracking signal corresponding to and tracking the propagation of the activation signal; and

activating the sense amplifiers in accordance with the propagation of the tracking signal.

12. The method of claim 11, wherein a duration of the tracking signal is not longer than the propagation time of the activation signal.

13. The method of claim 12, wherein a predetermined delay is introduced between the generation of the activation signal and the generation of the tracking signal.

14. A method of operating a memory circuit comprising the steps of:

propagating an activation signal along a word line of the memory circuit to activate the word line, the activation signal having a propagation time period associated with propagating the word line; and

sequentially activating a plurality of sense amplifiers connected to digit lines of the memory circuit prior to an expiration of the propagation time period of the activation signal.

15. The method of claim 14, wherein the sense amplifiers are sequentially activated in a direction from a first sense amplifier located closest to a front edge of the activated word line to a last sense amplifier located closest to a back edge of the activated word line.

16. The method of claim 14 further comprising the step of grouping the digit lines into blocks of digit lines, wherein each block comprises at least two digit lines.

17. The method of claim 16 further comprising the step of connecting each sense amplifier to a block of digit lines.

18. The method of claim 14, wherein said sequentially activating step comprises:

generating a tracking signal propagating along a dummy word line coupled to the memory circuit, the tracking signal corresponding to and tracking the propagation of the activation signal; and

activating the sense amplifiers in accordance with the propagation of the tracking signal.

19. The method of claim 18, wherein a duration of the tracking signal is not longer than the propagation time of the activation signal.

20. The method of claim 18, wherein a predetermined delay is introduced between the generation of the activation signal and the generation of the tracking signal.

21. A method of operating a memory circuit comprising the steps of:

providing a peak current reduction circuit coupled to a row decoder and digit lines of the memory circuit;

activating a word line coupled to the row decoder in the memory circuit by propagating an activation signal along the word line, the activation signal having a propagation time period associated with propagating the word line;

activating a dummy word line in the peak current reduction circuit by propagating a tracking signal along the dummy word line, the tracking signal corresponding to and tracking the propagation of the activation signal; and

sequentially activating a plurality of sense amplifiers connected to digit lines of the memory circuit in accordance with the tracking signal, wherein a duration of the sequential activation does not exceed the activation signal propagation time period.

22. The method of claim 21, wherein the sense amplifiers are sequentially activated in a direction from a first sense amplifier located closest to a front edge of the activated word line to a last sense amplifier located closest to a back edge of the activated word line.