Method for synchronizing a cycle master node to a cycle slave node using synchronization information from an external network or sub-network which is supplied to the cycle slave node

• US 6,128,318 A
• Filed: 01/23/1998
• Issued: 10/03/2000
• Est. Priority Date: 01/23/1998
• Status: Expired due to Term

• Current Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Sato, Takashi
• Primary Examiner(s): Vu, Huy D.
• Assistant Examiner(s): PHAN, MAN U
• Application Number:
  US09/012,321
• Time in Patent Office: 984 Days
• Field of Search: 370/503, 370/510, 370/507, 370/508, 370/516, 370/519, 395/553, 395/356, 395/358, 395/359, 395/200.78, 395/200.31, 375/356, 375/357
• US Class Current: 370/503
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: H04J 3/0652 Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40091 Bus bridging LAN interconnection over a bridge based backbone H04L12/462; single bridge functionality H04L12/462
• CPC Class Codes: H04N 21/4302 Content synchronisation processes, e.g. decoder synchronisation
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052

Abstract

A method for synchronizing a cycle master node to a cycle slave node, including the steps of utilizing logic circuitry in the cycle slave node to determine a timer offset value, in response to the cycle slave node receiving synchronization information, transmitting the timer offset value to the cycle master node, and, utilizing logic circuitry in the cycle master node to adjust a value of a cycle master node cycle timer on the basis of the timer offset value. The synchronization information is preferably a cycle reset signal that is asserted at a prescribed rate which is a multiple of one cycle of the cycle slave node cycle timer. The cycle master node and the cycle slave node can advantageously be included in a first network or sub-network and the cycle reset signal can be supplied by a second network or sub-network which is external to the first network or sub-network.

Claims

1. A method for synchronizing a cycle master node to a cycle slave node, including the steps of:

utilizing logic circuitry in the cycle slave node to determine a timer offset value, in response to the cycle slave node receiving synchronization information including a cycle reset signal, wherein determining the timer offset value includes calculating a number of clock cycles that have elapsed between a first time at which the cycle reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer; and

, and subtracting the result of the above calculating step from the value read out of the cycle slave node cycle timer, whereby the result of the subtracting step constitutes the timer offset value;

transmitting the timer offset value to the cycle master node; and

,

utilizing logic circuitry in the cycle master node to adjust a value of a cycle master node cycle timer on the basis of the timer offset value.

2. The method as set forth in claim 1, wherein:

the cycle slave node further includes a cycle timer which counts from an initial value to a final value during a cycle; and

,

the cycle reset signal is asserted at a prescribed rate which is a multiple of one cycle of the cycle slave node cycle timer.

3. The method as set forth in claim 2, wherein:

the cycle slave node further includes a timer offset register;

the cycle master node further includes a timer adjustment register;

the step of utilizing the logic circuitry in the cycle slave node to determine the timer offset value includes the sub-steps of;

detecting the cycle reset signal;

reading a value of the cycle slave node cycle timer;

deriving the timer offset value from the value read out of the cycle slave node cycle timer; and

,

loading the timer offset value into the timer offset register.

4. The method as set forth in claim 3, wherein the step of transmitting the timer offset value to the cycle master node includes the sub-steps of:

reading the timer offset value from the timer offset register; and

,

sending the timer offset value to the cycle master node using an asynchronous data transfer protocol.

5. The method as set forth in claim 3, wherein the step of utilizing the logic circuitry in the cycle master node to adjust a value of the cycle master node cycle timer includes the sub-steps of:

loading the timer offset value received from the cycle slave node into the timer adjustment register;

reading a value of the cycle master node cycle timer;

subtracting the timer offset value from the value read out of the cycle master node cycle timer to produce an adjusted cycle timer value;

deriving a final adjusted cycle timer value from the adjusted cycle timer value; and

,

loading the final adjusted cycle timer value into the cycle master node cycle timer.

6. The method as set forth in claim 5, wherein the sub-step of deriving the final adjusted cycle timer value includes the sub-steps of:

calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer; and

,

adding the result of the above calculating sub-step to the adjusted cycle timer value, whereby the result of the adding step is the final adjusted cycle timer value.

7. The method as set forth in claim 5, wherein the sub-step of deriving the timer offset value from the value read out of the cycle slave node cycle timer includes the sub-steps of:

calculating a number of clock cycles that have elapsed between a first time at which the cycle reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer; and

,

subtracting the result of the above calculating step from the value read out of the cycle slave node cycle timer, whereby the result of the subtracting step constitutes the timer offset value.

8. The method as set forth in claim 7, wherein the sub-step of deriving the final adjusted cycle timer value includes the sub-steps of:

calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer; and

,

adding the result of the above calculating sub-step to the adjusted cycle timer value, whereby the result of the adding step is the final adjusted cycle timer value.

9. The method as set forth in claim 1, wherein:

the cycle master node and the cycle slave node are part of a first network; and

,

the synchronization information is supplied by a second network that is external to the first network.

10. The method as set forth in claim 1, wherein:

the cycle master node and the cycle slave node are part of a first sub-network; and

,

the synchronization information is supplied by a second sub-network that is external to the first sub-network.

11. The method as set forth in claim 2, wherein:

the cycle master node and the cycle slave node are part of a first sub-network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first sub-network.

12. The method as set forth in claim 11, further including the step of regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first sub-network, whereby all of the cycle slave nodes in the first sub-network are synchronized to the cycle reset signal.

13. The method as set forth in claim 2, wherein:

the cycle master node and the cycle slave node are part of a first network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first network.

14. The method as set forth in claim 1, further including the step of regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first network, whereby the cycle timers of all of the cycle slave nodes in the first network are synchronized to the cycle reset signal.

15. The method as set forth in claim 8, wherein:

the cycle master node and the cycle slave node are part of a first sub-network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first sub-network.

16. The method as set forth in claim 15, further including the step of regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first sub-network, whereby all of the cycle slave nodes in the first sub-network are synchronized to the cycle reset signal.

17. The method as set forth in claim 8, wherein:

the cycle master node and the cycle slave node are part of a first network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first network.

18. The method as set forth in claim 17, further including the step of regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first network, whereby the cycle timers of all of the cycle slave nodes in the first network are synchronized to the cycle reset signal.

19. A system, including:

a cycle slave node which includes;

a cycle slave node cycle timer; and

,

cycle slave node logic circuitry;

a cycle master node which includes;

a cycle master node cycle timer; and

,

cycle master node logic circuitry;

wherein the cycle slave node logic circuitry is response to synchronization information that includes a cycle reset signal to determine a timer offset value by calculating a number of clock cycles that have elapsed between a first time at which the cycle reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer; and

, subtracting the result of the above calculation from the value read out of the cycle slave node cycle timer, whereby the result of the subtraction constitutes the timer offset value and to transmit the timer offset value to the cycle master node; and

,

wherein the cycle master node logic circuitry adjusts a value of the cycle master node cycle timer on the basis of the timer offset value.

20. The system as set forth in claim 19, wherein:

the cycle slave node cycle timer counts from an initial value to a final value during a cycle; and

,

the cycle reset signal is asserted at a prescribed rate which is a multiple of one cycle of the cycle slave node cycle timer.

21. The system as set forth in claim 20, wherein:

the cycle slave node further includes a timer offset register;

the cycle master node further includes a timer adjustment register;

the cycle slave node logic circuitry determines the timer offset value by;

detecting the cycle reset signal;

reading a value of the cycle slave node cycle timer;

deriving the timer offset value from the value read out of the cycle slave node cycle timer; and

,

loading the timer offset value into the timer offset register.

22. The system as set forth in claim 21, wherein the cycle slave node logic circuitry transmits the timer offset value to the cycle master node by:

reading the timer offset value from the timer offset register; and

,

sending the timer offset value to the cycle master node using an asynchronous data transfer protocol.

23. The system as set forth in claim 21, wherein the cycle master node logic circuitry adjusts the value of the cycle master node cycle timer by:

loading the timer offset value received from the cycle slave node into the timer adjustment register;

reading a value of the cycle master node cycle timer;

subtracting the timer offset value from the value read out of the cycle master node cycle timer to produce an adjusted cycle timer value;

deriving a final adjusted cycle timer value from the adjusted cycle timer value; and

,

loading the final adjusted cycle timer value into the cycle master node cycle timer.

24. The system as set forth in claim 23, wherein the cycle master node logic circuitry derives the final adjusted cycle timer value by:

calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer; and

,

adding the result of the above calculation to the adjusted cycle timer value, whereby the result of the addition is the final adjusted cycle timer value.

25. The system as set forth in claim 23, wherein the cycle slave node logic circuitry derives the timer offset value from the value read out of the cycle slave node cycle timer by:

calculating a number of clock cycles that have elapsed between a first time at which the cycle reset signal was detected and a second time at which the value was read out of the cycle slave node cycle timer; and

,

subtracting the result of the above calculation from the value read out of the cycle slave node cycle timer, whereby the the result of the subtraction constitutes the timer offset value.

26. The system as set forth in claim 25, wherein the cycle master node logic circuitry derives the final adjusted cycle timer value by:

calculating a number of clock cycles required to perform all required processing starting from a first time at which the value is read out of the cycle master node cycle timer and ending with a second time at which the final adjusted cycle timer value is loaded into the cycle master node cycle timer; and

,

adding the result of the above calculation to the adjusted cycle timer value, whereby the result of the addition is the final adjusted cycle timer value.

27. The system as set forth in claim 19, wherein:

the cycle master node and the cycle slave node are part of a first network; and

,

the synchronization information is supplied by a second network that is external to the first network.

28. The system as set forth in claim 19, wherein:

the cycle master node and the cycle slave node are part of a first sub-network; and

,

the synchronization information is supplied by a second sub-network that is external to the first sub-network.

29. The system as set forth in claim 20, wherein:

the cycle master node and the cycle slave node are part of a first sub-network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first sub-network.

30. The system as set forth in claim 29, further including means for regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first sub-network, whereby all of the cycle slave nodes in the first sub-network are synchronized to the cycle reset signal.

31. The system as set forth in claim 20, wherein:

the cycle master node and the cycle slave node are part of a first network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first network.

32. The system as set forth in claim 31, further including means for regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first network, whereby the cycle timers of all of the cycle slave nodes in the first network are synchronized to the cycle reset signal.

33. The system as set forth in claim 32, further including means for regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first sub-network, whereby all of the cycle slave nodes in the first sub-network are synchronized to the cycle reset signal.

34. The system as set forth in claim 26, wherein:

the cycle master node and the cycle slave node are part of a first network which also includes a plurality of additional cycle slave nodes; and

,

the cycle reset signal is synchronously supplied by a second sub-network that is external to the first network.

35. The system as set forth in claim 34, further including means for regularly distributing the value of the cycle master node cycle timer to all of the cycle slave nodes in the first network, whereby the cycle timers of all of the cycle slave nodes in the first network are synchronized to the cycle reset signal.

36. A network, including:

a first sub-network which includes a plurality of first nodes connected to a first local bus;

a second sub-network which includes a plurality of second nodes connected to a second local bus;

a bridge which interconnects the first and second sub-networks, wherein the bridge includes;

a first bridge portal coupled to the first local bus;

a second bridge portal coupled to the second local bus; and

,

an interconnect system which interconnects the first and second bridge portals; and

,

wherein a selected one of the first nodes which serves as a local cycle master of the first sub-network is a non-bridge node and wherein the first bridge portal contains a cycle slave node like the one defined in claim 23 and, the local cycle master for the first sub-network comprises a cycle master node like the one defined in claim 23.

37. The network as set forth in claim 36, wherein a selected one of the second nodes which serves as a local cycle master of the second sub-network is a non-bridge node.

38. The network as set forth in claim 37, wherein:

the second bridge portal contains a cycle slave node like the one defined in claim 26; and

,

the local cycle master for the second sub-network comprises a cycle master node like the one defined in claim 23.