Software rate adaptable modem with forward compatible and expandable functionality and method of operation

• US 6,128,335 A
• Filed: 06/30/1997
• Issued: 10/03/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Integrated Telecom Express, Inc.
• Inventors: Chen, Steve, Liu, Ming-Kang, Liu, Young Way
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US08/884,957
• Time in Patent Office: 1,191 Days
• Field of Search: 375/219, 375/220, 375/222, 375/260, 375/316, 375/354, 375/200.63, 347/251, 364/148, 364/705.05, 370/94.2, 370/445, 370/480, 370/485, 370/492, 379/93.14, 455/522
• US Class Current: 375/220
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A high speed software modem is described which uses a selectable, desirable portion of the total available bandwidth of a transmission channel. In a preferred embodiment, the invention is implemented in a personal computer connected to an upstream transceiver through a channel supporting an Asymmetric Digital Subscriber Loop (ADSL) standard. The achievable target data rate of the modem is based on the capabilities of an analog front end (AFE) used in the modem, and a host processor within such personal computer. In particular, the modem AFE contains subband filtering which causes an upstream transceiver to use only a selected number of available sub-channels for downstream data transmission. The data rate of the modem is increased by upgrading the AFE or the host processor in order to increase the number of processable transmitted downstream sub-channels.

Claims

1. A high speed communications transciever for communicating with an upstream transciever transmitting an analog signal using M data carrying signals within a bandwidth F through a channel to said system, said transceiver comprising:

a channel interface circuit for coupling to and receiving said analog signal from the channel; and

a front end receiving circuit for sampling the analog signal and generating a digital signal based on such analog signal, the digital signal including data from a first frequency bandwidth portion f1 of said bandwidth F containing N data carrying signals, where N<

M; and

a front end transmitting circuit for transmitting control information to cause said upstream transceiver to transmit downstream data only using the N data carrying signals, said control information indicating to the upstream transceiver that;

(i) only N of the M data carrying signals are desirable for downstream data transmission, even if said channel is capable of supporting more than N data carrying signals; and

(ii) the system supports any transmission protocols used by said upstream transceiver; and

(iii) that they are connected through a channel which should be treated by said upstream transceiver as having substantial signal attenuation characteristics for data signals other than the N data carrying signals; and

a bus interface circuit for transmitting the digital signal to a host processing device.

2. The transceiver of claim 1, further including a host processor circuit in the host processing device for extracting selected data from the N data carrying signals.

3. The transceiver of claim 2, wherein the selection of the N data carrying signals can be made by the host processor circuit based in part on sampling capabilities of the front end receiving circuit.

4. The transceiver of claim 3, wherein the selection of the N data carrying signals is made by the host processor circuit based in part on the processing capabilities available to the host processor circuit.

5. The transceiver of claim 4, wherein the selection of the N data carrying signals can be performed by a calibration routine executed by the host processor circuit to determine the processing capabilities available to the host processor circuit.

6. The transceiver of claim 5, wherein the N data carrying signals can be determined by a user of the host processing device based on system parameter options presented to the user by an applications program running on the host processing device, and this selection can be confirmed by a verification routine executed by the host processing device.

7. The system of claim 1, wherein the selected data further includes data obtained from an additional second frequency bandwidth portion f2 of said bandwidth F, so that an additional number of data carrying signals P from the M data carrying signals (N+P<

M) can be transmitted by the bus interface circuit to be processed by the host processor circuit.

8. The system of claim 1, wherein the front end receiving circuit includes:

(i) a bandpass filter for passing the first frequency bandwidth portion fl of said bandwidth F;

(ii) and an analog to digital converter; and

wherein the bus interface circuit transmits the N data carrying signals to a host processor circuit that includes a host microprocessor, a programmable memory coupled to the microprocessor, and a data extraction routine located in the memory which can be executed by the microprocessor.

9. The system of claim 8, wherein a data received rate of the system can be increased by upgrading the host microprocessor with a second microprocessor which has increased signal processing capabilities, and coupling this second microprocessor to the bus interface circuit.

10. The system of claim 8, wherein the front end receiving circuit has a programmable frequency response.

11. The system of claim 1, further including a front end transmitting circuit for transmitting an upstream data transmission using a second frequency bandwidth F2 different from F, and L upstream data carrying signals, and where L<

M.

12. A high speed communications system for receiving selected data contained in a number of modulated sub-channels N from an upstream transceiver capable of transmitting a number of modulated sub-channels M through a channel to said system using an analog signal, said system comprising:

a channel interface circuit for coupling to and receiving said analog signal from the channel;

an analog front end circuit for sampling the analog signal and converting it to a digital signal, the front end circuit including an anti-aliasing filter and an analog to digital converter, and the digital signal including data only from said number of sub-channels N, where N<

=M,

a bus interface circuit for transmitting the N sub-channels to a host processing device so that selected data can be demodulated from the N sub-channels;

a front end transmitting circuit for transmitting control information to cause said upstream transceiver to transmit downstream data only using the N sub-channels, said control information being used for;

(i) permanently masking out all the available sub-channels except the N sub-channels for any subsequent downstream data transmission from said upstream transceiver; and

further indicating that;

(ii) the system supports any data transmission protocols used by the upstream transceiver; and

(iii) also indicating that the system and upstream transceiver are connected through a channel which should be treated as having substantial signal attenuation characteristics for sub-channels other than the N sub-channels.

13. The system of claim 12, wherein the number of sub-channels N to be demodulated is based in part on sampling capabilities of the analog front end receiving circuit.

14. The system of claim 13, wherein the number of sub-channels N to be demodulated is selected by the host processing device based in part on the processing capabilities available to the host processing device.

15. The system of claim 14, wherein the selection of the number of sub-channels N can be N can be performed by a calibration routine executed by the host processing evice to determine the processing capabilities available to the host processing device.

16. The system of claim 14, wherein the number of sub-channels N can be determined by a user of the host processing device based on system parameter options presented to the user by an application program running on the host processing device, and this selection can be confirmed by a verification routine executed by the host processing device.

17. The system of claim 12, wherein the N sub-channels are selected by the host processor circuit based on data carrying capacities of the M available sub-channels.

18. The system of claim 12, wherein the selected data further includes data obtained from an additional second number of sub-channels P, so that an additional number of sub-channels (N+P<

M) can be demodulated.

19. The system of claim 18, wherein the analog front end receiving circuit has a programmable frequency response that determines which of the N-sub channels are to be passed from the M available sub-channels.

20. The system of claim 12, wherein the analog front end receiving circuit includes:

(i) a bandpass filter for passing the N sub-channels; and

(ii) an analog to digital converter; and

wherein the bus interface is configured to be coupled to a host processor circuit that includes a host microprocessor, a programmable memory coupled to the microprocessor, and a demodulation routine located in the memory which can be executed by the microprocessor.

21. The system of claim 20, wherein a received data rate of the system can be controlled by controlling the processing power of a host microprocessor in the host processing device coupled to the bus.

22. The system of claim 12, wherein the upstream transceiver uses discrete multi-tone (DMT) modulation for generating the M modulated sub-channels, and the upstream transceiver perceives that the system:

(i) supports asymmetric digital subscriber loop (ADSL) transmission protocols;

(ii) is comparable with T1.413 standards using a reduced number of sub-channels and a reduced data rate.

23. The system of claim 12, further including a front end transmitting circuit for transmitting an upstream data transmission using a second set of modulated sub-channels L separate from the M sub-channels, and where L<

M.

24. A high speed communications data receiver for receiving data at a rate X through a channel from an upstream transceiver capable of transmitting a data stream at a rate Y, the receiver comprising:

a channel interface circuit for coupling to and receiving said data stream having said rate Y; and

an analog front end circuit for data sampling a portion of the analog signal and converting it to a digital signal having said data rate X; and

a bus interface circuit for transmitting the digital signal at said rate X to a host processing device, and for receiving a transmission control signal from the host processing device to cause said upstream transmitter to transmit at a data rate substantially equal to said data rate X during any data stream transmission; and

a transmitting circuit for transmitting control information to cause said upstream transceiver to transmit downstream data using a set of N data carrying signals, which N data carrying signals constitute a subset of M signals available for carrying data in the channel, said control information including feedback information from the host processing device indicating to the upstream transceiver that;

(i) only N of the M data carrying signals are desirable for downstream data transmission, even if said channel is capable of supporting more than N data carrying signals; and

(ii) the receiver supports any upstream transceiver data transmission protocols; and

(iii) that they are connected through a channel which should be treated by said upstream transceiver as having substantial signal attenuation characteristics for data signals other than the N data carrying signals; and

wherein data sampling circuitry requirements of the analog front end are reduced because data sampling is only performed for a fractional portion k of the data stream, where k=M/N.

25. The system of claim 24, wherein the analog front end circuit further includes an anti-aliasing filter for filtering the analog data signal to generate the fractional portion of the data stream that requires data sampling and extracting.

26. The system of claim 24, wherein an upstream data transmission uses a second set of data carrying signals L separate from the M data carrying signals, and where L<

M.

27. The system of claim 24, wherein the ratio of X to Y is approximately 0.5 or less, and this ratio can be increased through modular additions to the analog front end circuit.

28. A method of operating a high speed communications system that is coupled to a host processing device and an upstream transceiver through a channel capable of supporting an analog data transmission signal having a bandwidth F, said method comprising:

(a) configuring said system to achieve a receive data rate X; and

(b) receiving an analog initialization signal having a bandwidth F from the upstream transceiver through the channel; and

(c) generating a digital signal based on sampling a portion of the analog initialization signal corresponding to a first frequency bandwidth portion f1 sufficient to meet receive data rate X; and

(d) transmitting the digital signal to a signal processing circuit, so that characteristics of data carrying signals contained within first frequency bandwidth portion f1 can be determined; and

(e) generating feedback information indicating to the upstream transceiver that bandwidth other than the first frequency bandwidth f1 should not be used for data transmission, said feedback information further indicating that;

(i) only N out of M available data carrying signals are desirable for downstream data transmission, where N<

M/k, and k is an integer, even if said channel is capable of supporting more than N data carrying signals; and

(ii) the system supports any transmission protocols used by the upstream transceiver; and

(iii) that they are connected through a channel which should be treated by said upstream transceiver as having substantial signal attenuation characteristics for data signals other than the N data carrying signals; and

(f) receiving an analog data transmission signal having a bandwidth f1 from said upstream transceiver; and

(g) generating a digital signal based on sampling the analog data transmission signal; and

(h) transmitting the digital signal to the host processing device so that it can be processed to extract selected data from the data carrying signals.

29. The method of claim 28, further including a step:

determining an optimal size and location of first frequency bandpass portion f1 so as to minimize the amount of processing required to extract the data from the digital signal.

30. The method of claim 28, wherein the system transmits feedback information containing intentionally altered channel characteristic information.

31. The method of claim 28, wherein the M data signals include M modulated sub-channels, and the selected data is contained in N of the M sub-channels.

32. The method of claim 31, further including a step:

determining an optimal set of N sub-channels so as to minimize the amount of processing required to extract the data from the digital signal.

33. The method of claim 32, further including a step wherein data protocol information pertaining Asymmetric Digital Subscriber Loops is transmitted by the upstream data transceiver so as to set up an ADSL compatible data link, which ADSL compatible data link uses a reduced number of sub-channels and a reduced data rate from that available using full rate T1.413 standards.

34. A high speed communications system for processing an analog data signal from a channel capable of supporting M modulated sub-channels, said system comprising:

a channel interface circuit for coupling to and receiving said analog data signal from the channel;

an analog front end circuit for processing the analog data signal and converting it to a digital signal;

a processing circuit for extracting data from the digital signal, the digital signal including data taken from a number N of said sub-channels, where N is intentionally selected to have a value less than M, and where N is negotiated with a remote transceiver during an initialization procedure; and

further wherein during said initialization procedure, feedback information from the processing circuit indicates to said remote transceiver that;

(i) only N of the M data sub-channels are to be used for data transmission, even if said channel is capable of supporting more than N sub-channels; and

(ii) the system supports any data protocols used by the remote transceiver, including xDSL based protocols, so that a reduced rate but otherwise compatible version of such xDSL based protocols can be used in the channel; and

(iii) that they are connected through a channel which should be treated by said remote transceiver as having substantial signal attenuation characteristics for sub-channels other than the N sub-channels.

35. The system of claim 34, where the N sub-channels are initially loaded with bit capacities that are left essentially unchanged unless transmission characteristics of said channel vary.

36. The system of claim 34, wherein the selection of the N sub-channels can be done during the initialization procedure.

37. The system of claim 34, wherein the value of N is based on signal processing capability of the processing circuit.

38. The system of claim 34, wherein a target data rate of the system can be increased by processing an additional number of sub-channels P from the M sub-channels, and where N+P<

M.

39. The system of claim 34 further including a front end transmitting circuit for transmitting said feedback information.

40. The system of claim 34, wherein the upstream transceiver uses discrete multi-tone (DMT) modulation for generating the M modulated sub-channels, and the channel supports asymmetric digital subscriber loop (ADSL) transmission protocols.

41. A high speed communications system for processing an analog data signal from a channel capable of supporting M modulated sub-channels, said system comprising:

a channel interface circuit for coupling to and receiving said analog data signal from the channel;

an analog front end circuit for processing the analog data signal and converting it to a digital signal;

a bus interface circuit for transmitting the digital signal to a host processing device, and for receiving a transmission control signal from the host processing device to cause a remote transmitter to transmit using only a number N of said sub-channels, where N is intentionally selected to have a value less than M, and where N is negotiated with an upstream transceiver during an initialization procedure; and

wherein said transmission control signal further specifies that;

(i) only N of the M sub-channels are desirable for downstream data transmission, even if said channel is capable of supporting more than N sub-channels; and

(ii) the system supports any data protocols used by the remote transmitter for transmitting data in said channel, including xDSL based protocols, so that a reduced rate but otherwise compatible version of such xDSL based protocols can be used in the channel; and

(iii) that they are connected through a channel which should be treated by said remote transmitter as having substantial signal attenuation characteristics for sub-channels other than the N sub-channels.

42. The system of claim 41, wherein the value of N is based on signal processing capability of the host processing device.

43. The system of claim 41, wherein a data rate of the system can be increased by processing an additional number of sub-channels P from the M sub-channels, and where N+P<

M.

44. The system of claim 41, wherein the upstream transceiver uses discrete multi-tone (DMT) modulation for generating the M modulated sub-channels, and the channel supports a T1.413 compatible data link using asymmetric digital subscriber loop (ADSL) transmission protocols.

45. A method of processing an xDSL signal from a digital subscriber loop, said method including the steps of:

negotiating a reduced data rate R'"'"' for said signal between a downstream and an upstream transceiver; and

processing feedback information from the downstream transceiver indicating that;

(i) only N out of M sub-channels available to the upstream transceiver are desirable for downstream data transmission, where N<

=M/k, and k is an integer, even if said channel is capable of supporting more than N sub-channels; and

(ii) the downstream transceiver supports any data protocols, including xDSL based protocols used for data transmission by the upstream transceiver, so that the upstream transceiver perceives that said downstream transceiver is fully compliant with T1.413 standards, but with a reduced number of sub-channels from that available using a full rate ADSL transceiver; and

(iii) they are connected through a channel which should be treated by said upstream transceiver as having substantial signal attenuation characteristics for sub-channels other than said N sub-channels; and

thereafter transmitting said xDSL signal from the upstream transciever to the downstream transceiver utilizing said sub-channels N to effectuate the reduced data rate R'"'"', where N is intentionally selected to be less than a maximum number of said sub-channels M supported by said digital subscriber loop;

wherein the number of sub-channels N is based on signal processing capability available to the downstream transceiver.

46. The method of claim 45, wherein the data rate of the system can be increased by processing an additional number of sub-channels P from the M sub-channels, and where N+P<

M.

47. The method of claim 45, wherein the upstream transceiver uses discrete multi-tone (DMT) modulation for generating the M sub-channels.

48. The method of claim 45, wherein the reduced data rate R'"'"' can be specified by a user operating the downstream transceiver.

49. A method of processing an xDSL signal from a digital subscriber loop, said method including the steps of:

negotiating a reduced data rate R'"'"' for said signal between a downstream and an upstream transceiver; and

processing feedback information from the downstream transceiver indicating that;

(i) only N out of M sub-channels available to the upstream transceiver are desirable for downstream data transmission, where N<

=M/k, and k is an integer, even if said channel is capable of supporting more than N sub-channels; and

(ii) the downstream transceiver supports any data protocols including xDSL based protocols used for data transmission by the upstream transceiver so that the upstream transceiver perceives that said downstream transceiver is fully compliant with T1.413 standards, but with a reduced number of sub-channels from that available using a full rate ADSL transceiver; and

(iii) they are connected through a channel which should be treated by said upstream transceiver as having substantial signal attenuation characteristics for sub-channels other than said N sub-channels; and

thereafter transmitting said xDSL signal from the upstream transciever to the downstream transceiver utilizing a frequency bandwidth f1 to carry said N sub-channels and to effectuate the reduced data rate R'"'"', where f1 is intentionally selected to be less than a maximum bandwidth F supported by said digital subscriber loop; and

wherein the frequency bandwidth f1 is based on signal processing capability available to the downstream transceiver.

50. The system of claim 49, wherein the value of f1 is based on signal processing capability of a host processing device.

51. The system of claim 49, wherein a target data rate of the system can be increased by processing an additional frequency bandwidth f2, and where f1+f2<

F.

52. The system of claim 49, wherein the channel supports asymmetric digital subscriber loop (ADSL) transmission protocols.