Method and apparatus for communication and translation of a plurality of digital protocols

• US 6,128,673 A
• Filed: 11/14/1997
• Issued: 10/03/2000
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Joel Silverman, Michael D. Aronson
• Inventors: Silverman, Joel, Aronson, Michael D.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/970,736
• Time in Patent Office: 1,054 Days
• Field of Search: 710/62-65, 710/72-73, 710/20-23, 710/31, 710/33, 710/128-129, 710/70, 710/69, 710/105, 710/106, 710/10, 710/12, 710/16
• US Class Current: 710/22
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function

Abstract

A digital protocol translator including a first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, the first protocol circuitry including a first controller. The translator further includes a second protocol circuitry having a second I/O port communicating using a second digital protocol different from the first digital protocol, the second protocol circuitry including a second controller in communication with the first controller, such that communications between the first I/O port and the second I/O port are translated between the first protocol and the second protocol. Preferably, the translator further includes a microprocessor and digital memory, where the microprocessor operates under the control of a program stored in the memory. Also preferably, the first controller includes a first state machine, a first plurality of registers, and a first DMA interface, and the second controller includes a second state machine, a second plurality of registers, and a second DMA interface.

Claims

1. A single chip digital protocol translator comprising;

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol;

wherein said first protocol circuitry and said second protocol circuitry are integrated on a single chip; and

a digital microprocessor and digital memory integrated on said chip, said digital memory being coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said digital memory and communicating with both said first controller and said second controller.

3. A digital protocol translator as recited in claim 1 wherein said digital memory includes both fixed memory and read/write memory.

7. A digital protocol translator as recited in claim 3 wherein microprocessor instructions defining a plurality of protocols are stored within said read/write memory.

2. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol; and

wherein said first controller includes a first DMA interface and a first state machine separate from and communicating with said first DMA interface.

4. A digital protocol translator as recited in claim 2, wherein said second controller includes a second DMA interface and a second state machine separate from and communicating with said second DMA interface.

5. A digital protocol translator as recited in claim 2, wherein said first controller further includes a plurality of registers communicating with said first state machine.

6. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

a digital microprocessor and semiconductor digital memory coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said semiconductor digital memory and communicating with both said first controller and said second controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol; and

wherein said semiconductor digital memory includes fixed memory and microprocessor program instructions defining a plurality of protocols are stored within said fixed memory.

8. A digital protocol translator as recited in claim 6, wherein said first protocol circuitry, said second protocol circuitry, said digital microprocessor and said semiconductor digital memory are integrated on a single chip.

9. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

a digital microprocessor and semiconductor memory coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said semiconductor memory and communicating with both said first controller and said second controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol; and

wherein said semiconductor memory includes semiconductor read/write memory, and wherein microprocessor program instructions defining a plurality of protocols are loaded into said semiconductor read/write memory through at least one of said first I/O port and said second I/O port, and wherein said first protocol circuitry, said second protocol circuitry, said digital microprocessor, and said semiconductor memory are integrated on a single chip.

10. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port communicating using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol; and

wherein said first protocol is a USB protocol, and wherein said second protocol is an Ethernet protocol.

11. A digital protocol translator as recited in claim 10 wherein said first protocol circuitry and said second protocol circuitry are integrated on a single chip.

12. A digital translator as recited in claim 10, wherein said first protocol circuitry includes a first DMA interface and a first state machine separate from and communicating with said first DMA interface.

13. A digital protocol translator as recited in claim 10 farther comprising a digital memory and wherein said first controller includes a first DMA interface capable of accessing said digital memory and said second controller includes a second DMA interface capable of accessing said digital memory.

14. A digital protocol translator as recited in claim 10 further comprising a digital microprocessor and semiconductor memory coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said semiconductor memory and communicating with both said first controller and said second controller, and wherein said semiconductor memory includes semiconductor fixed memory and wherein microprocessor program instructions defining a plurality of protocols are stored within said semiconductor fixed memory.

15. A digital protocol translator as recited in claim 10 further comprising a digital microprocessor and semiconductor memory coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said semiconductor memory and communicating with both said first controller and said second controller, and wherein said semiconductor memory includes semiconductor read/write memory and wherein microprocessor program instructions defining a plurality of protocols are loaded into said semiconductor read/write memory through at least one of said first I/O port and said second I/O port.

16. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

a cable assembly including a first connector, a second connector, and a cable extending between said first connector and said second connector, wherein said first protocol circuitry and said second protocol circuitry are located within said cable assembly and

whereby said communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol.

17. A digital protocol translator as recited in claim 16 wherein at least one of said first protocol circuitry and said second protocol circuitry are located within one of said first connector and said second connector.

18. A digital protocol translator as recited in claim 16 wherein at least one of said first protocol circuitry and said second protocol circuitry are located within said cable of said cable assembly.

19. A digital protocol translator as recited in claim 18 wherein said at least one of said first protocol circuitry and said second protocol circuitry are located within a dongle forming a part of said cable of said cable assembly.

20. A method for translating digital communications comprising:

receiving into a first protocol circuitry a first digital communication using a first digital protocol;

processing said first digital communication within said first protocol circuitry under a direction of a first controller;

receiving into a second protocol circuitry a processed first digital communication output of said first protocol circuitry;

processing said processed first digital communication output within said second protocol circuitry;

outputting a translated first digital communication from said second protocol circuitry; and

wherein said first digital protocol is a USB protocol and wherein said second digital protocol is an Ethernet protocol.

21. A method of translating digital communications as recited in claim 20 further comprising:

receiving into said second protocol circuitry a second digital communication using said second digital protocol;

processing said second digital communication within said second protocol circuitry under a direction of a second controller;

receiving into said first protocol circuitry a processed second digital communication output of said second protocol circuitry;

processing said processed second digital communication output within said first protocol circuitry; and

outputting a translated second digital communication from said first protocol circuitry.

22. A method of translating digital communications as recited in claim 20 further comprising:

processing program instructions within a digital microprocessor coupled to said first protocol circuitry and said second protocol circuitry to coordinate and control the translating process, said program instructions being stored in a memory coupled to said digital microprocessor.

24. A method for translating digital communications as recited in claim 22 wherein said program instructions are stored, at least in part, within a read/write memory.

23. A method for translating digital communications comprising:

receiving into a first protocol circuitry a first digital communication using a first digital protocol,

processing said first digital communication within said first protocol circuitry under a direction of a first controller;

receiving into a second protocol circuitry a processed first digital communication output of said first protocol circuitry;

processing said processed first digital communication output within said second protocol circuitry;

outputting a translated first digital communication from said second protocol circuitry;

processing microprocessor program instructions defining a plurality of protocols within a digital microprocessor coupled to said first protocol circuitry and;

said second protocol circuitry; and

wherein said microprocessor program instructions are stored within a semiconductor fixed memory.

25. A method for translating digital communications comprising:

receiving into a first protocol circuitry through a first I/O port a first digital communication using a first digital protocol;

processing said first digital communication within said first protocol circuitry under a direction of a first controller;

receiving into a second protocol circuitry a processed first digital communication output of said first protocol circuitry;

processing said processed first digital communication output within said second protocol circuitry;

outputting a translated digital communication from said second protocol circuitry through a second I/O port; and

processing microprocessor program instructions defining a plurality of protocols within a digital microprocessor coupled to said first protocol circuitry and said second protocol circuitry;

wherein said microprocessor program instructions are loaded into a semiconductor read/write memory through at least one of said first I/O port and said second I/O port.

26. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry including a first controller;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry including a second controller in communication with said first controller;

a digital microprocessor and digital memory coupled to said digital microprocessor, said digital microprocessor operating under program control stored in said digital memory and communicating with both said first controller and said second controller;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol; and

wherein said first digital protocol is a USB protocol and wherein said second digital protocol is an Ethernet protocol.

27. A digital protocol translator comprising:

first protocol circuitry having a first I/O port adapted to communicate using a first digital protocol, said first protocol circuitry comprising a first controller including a first DMA interface;

second protocol circuitry having a second I/O port adapted to communicate using a second digital protocol different from said first digital protocol, said second protocol circuitry comprising a second controller in communication with said first controller, said second controller including a second DMA interface; and

a digital memory capable of being accessed both by the first and the second DMA interface;

whereby communications between said first I/O port and said second I/O port are translated between said first protocol and said second protocol.

28. A digital protocol translator as recited in claim 27, wherein said first protocol circuitry has a first state machine separate from and communicating with said first DMA interface.

29. A digital protocol translator as recited in claim 28, wherein said second protocol circuitry has a second state machine separate from and communicating with said second DMA interface.

30. A digital protocol translator as recited in claim 27, wherein said first protocol circuitry, said second protocol circuitry and said digital memory are integrated on a single chip.

31. A method for translating digital communications comprising:

receiving into a first protocol circuitry a first digital communication using a first digital protocol;

processing said first digital communication within said first protocol circuitry under a direction of a first state machine within a first controller;

sending a processed first digital communication output of said first protocol circuitry via a first DMA interface, wherein and said first state machine is separate from and communicating with said first DMA interface;

receiving into a second protocol circuitry said processed first digital communication output of said first protocol circuitry;

processing said processed first digital communication output within said second protocol circuitry under a direction of a second controller; and

outputting a translated digital communication from said second protocol circuitry.

32. A method for translating digital communications as recited in claim 31, wherein said receiving into a second protocol circuitry is performed via a second DMA interface, wherein and said second state machine is separate from and communicating with said second DMA interface, and said processing of said processed first digital communication output is performed under the direction of a second state machine within said second controller.

33. A method for translating digital communications comprising:

receiving into a first protocol circuitry a first digital communication using a first digital protocol;

processing said first digital communication within said first protocol circuitry under a direction of a first controller;

sending a processed first digital communication output of said first protocol circuitry via a first DMA interface to a digital memory;

receiving into a second protocol circuitry said processed first digital communication output from said digital memory via a second DMA interface;

processing said processed first digital communication output within said second protocol circuitry under a direction of a second controller; and

outputting a translated digital communication from said second protocol circuitry.

34. A method for translating digital communications as recited in claim 33, wherein said processing of said first digital communication is performed under the direction of a first state machine within said first controller.

35. A method for translating digital communications as recited in claim 34, wherein said processing of said processed first digital communication output is performed under the direction of a second state machine within said second controller.