Memory device having plurality of flash memories with a flash memory controlling circuit

• US 6,128,675 A
• Filed: 04/10/1998
• Issued: 10/03/2000
• Est. Priority Date: 04/10/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ko, Young-Hoon
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/058,353
• Time in Patent Office: 907 Days
• Field of Search: 710/22, 710/23, 710/9, 710/26, 711/103, 711/112, 365/200, 365/201, 365/185.33, 365/218, 395/431
• US Class Current: 710/23
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory device with a small computer system interface reads and writes mass data at high speed. The memory device includes a plurality of flash memories and a control circuit for allowing the flash memories to write and read data by page and to erase the data by block.

Claims

1. A memory device for use in a system providing mass data, comprising:

connector means including a small computer system interface (SCSI) for connecting said memory device to the system;

a plurality of flash memories;

direct memory access (DMA) controller means connected to said connector means via an address bus, a control bus and a data bus, and to said flash memories via said data bus, for controlling data access and transmission therebetween; and

flash memory control circuit means connected to said data bus, said address bus said control bus and said flash memories for writing and reading data to and from the flash memories by page.

2. The memory device as claimed in claim 1, wherein said flash memory control circuit means erases the data in the flash memories by block.

3. The memory device as claimed in claim 1, further comprising memory means connected to said address bus, said control bus and said data bus, for temporarily storing the data transferred between the connector means and the flash memories.

4. The memory device as claimed in claim 3, wherein said memory means comprises a non-volatile random access memory.

5. The memory device as claimed in claim 3, wherein said memory means delivers the data to said flash memories under the control of said DMA controller means.

6. The memory device as claimed in claim 1, further comprising address decoder means connected to said address bus and said control bus, for decoding an address signal received through said address bus, and for transmitting decoded output signals to at least one of said connector means and said flash memory control circuit means.

7. The memory device as claimed in claim 6, wherein said flash memory control circuit means responds to a selection signal received from said address decoder means for writing data into the flash memories.

8. The memory device as claimed in claim 6, wherein said flash memory control circuit means responds to a selection signal received from said address decoder means for reading data stored in said flash memories.

9. The memory device as claimed in claim 6, wherein said flash memory control circuit means comprises a latch circuit for latching address signals and a data signal in response an output signal from said decoder means.

10. The memory device as claimed in claim 9, further comprising reset signal generator means for generating a reset signal, said latch circuit being reset in response to said reset signal.

11. The memory device as claimed in claim 6, wherein said flash memory control circuit means comprises a decoder for decoding address signals, and for outputting decoded signals, said decoder being enabled in response to a selection signal provided by said address decoder means.

12. The memory device as claimed in claim 11, said flash memory control circuit means further comprising a flip-flop connected to said decoder for receiving an output signal therefrom, said flip-flop having an output for providing an address latch enable signal.

13. The memory device as claimed in claim 12, wherein said flip-flop has a clock input connected to said decoder for receiving an output signal therefrom.

14. The memory device as claimed in claim 6, wherein said flash memory control circuit means further comprises a decoder circuit and an inverter connected thereto, said inverter being connected to said address decoder means for receiving and inverting a selection signal therefrom.

15. The memory device as claimed in claim 14, wherein said flash memory control circuit means further comprises a counter connected to an output of said inverter, said counter being enabled to perform a counting operation in response to an output signal from said inverter.

16. The memory device as claimed in claim 15, wherein said flash memory control circuit means further comprises output circuitry connected to an output of said counter for receiving a count value from said counter, and being responsive thereto for generating at least one of a read enable signal and a write enable signal.

17. The memory device as claimed in claim 16, wherein said output circuitry comprises an AND gate connected to the output of said counter and producing a first output, and a plurality of NAND gates connected to said AND gate and to said decoder circuit for generating said read enable signal and said write enable signal.

18. The memory device as claimed in claim 6, wherein said flash memory control circuit means comprises a decoder circuit producing an output signal, and an inverter circuit for receiving and inverting said output signal from said decoder circuit so as to generate a command latch enable signal.

37. The memory device claimed in claim 1, wherein:

said flash memory control circuit means selects one of said flash memories, said selected one of said flash memories having a base address;

at least one address is latched by incrementing the base address by a given value;

a desired data operation is performed; and

one of the flash memories is released by setting the base address to a predetermined value.

38. The memory device as claimed in claim 37, wherein a read command is latched after said one of said flash memories is selected.

39. The memory device as claimed in claim 37, wherein said desired data operation comprises reading data of one page.

40. The memory device as claimed in claim 37, wherein a serial data input command is latched by incrementing the base address by a given value after said one of said flash memories is selected.

41. The memory device as claimed in claim 37, wherein said desired data operation comprises writing data of one page.

42. The memory device as claimed in claim 37, wherein a program command is latched by incrementing the base address by a given value, and then waiting, after said one of said flash memories is selected.

43. The memory device as claimed in claim 37, wherein a state read command is latched by incrementing the base address by a given value, and then reading a state byte, after said one of said flash memories is selected.

44. The memory device as claimed in claim 37, wherein a block erase setup command is latched by incrementing the base address by a given value after said at least one address is latched.

45. The memory device as claimed in claim 37, wherein an erase command is latched by incrementing the base address by a given value after said at least one address is latched, and wherein said desired data operation comprises a data erase operation.

46. The memory device as claimed in claim 37, wherein a state read command is latched by incrementing the base address by a given value, and reading a state byte, after said one of said flash memories is selected.

19. A memory device for use in a system providing mass data, comprising:

connector means including a small computer system interface (SCSI) for connecting said memory device to the system;

a plurality of flash memories; and

flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories;

wherein said flash memory control circuit means comprises a decoder for decoding address signals, and for outputting decoded signals, said decoder being enabled in response to a selection signal provided by said address decoder means.

20. The memory device as claimed in claim 19, said flash memory control circuit means further comprising a flip-flop connected to said decoder for receiving an output signal therefrom, said flip-flop having an output for providing an address latch enable signal.

21. The memory device as claimed in claim 20, wherein said flip-flop has a clock input connected to said decoder for receiving an output signal therefrom.

22. A memory device for use in a system providing mass data, comprising:

connector means including a small computer system interface (SCSI) for connecting said memory device to the system;

a plurality of flash memories;

flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories; and

address decoder means connected to said connector means and to said flash memory control circuit means for decoding an address signal received through an address bus, and for transmitting decoded output signals to at least one of said connector means and said flash memory control circuit means;

wherein said flash memory control circuit means further comprises a decoder circuit and an inverter connected thereto, said inverter being connected to said address decoder means for receiving and inverting a selection signal therefrom.

23. The memory device as claimed in claim 22, wherein said flash memory control circuit means further comprises a counter connected to an output of said inverter, said counter being enabled to perform a counting operation in response to an output signal from said inverter.

24. The memory device as claimed in claim 23, wherein said flash memory control circuit means further comprises output circuitry connected to an output of said counter for receiving a count value from said counter, and being responsive thereto for generating at least one of a read enable signal and a write enable signal.

25. The memory device as claimed in claim 24, wherein said output circuitry comprises an AND gate connected to the output of said counter and producing a first output, and a plurality of NAND gates connected to said AND gate and to said decoder circuit for generating said read enable signal and said write enable signal.

26. A memory device for use in a system providing mass data, comprising:

connector means including a small computer system interface (SCSI) for connecting said memory device to the system;

a plurality of flash memories; and

flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories;

wherein said flash memory control circuit means comprises a decoder circuit producing an output signal, and an inverter circuit for receiving and inverting said output signal from said decoder circuit so as to generate a command latch enable signal.

27. A method for auxiliary storage of mass data provided by a system via a small computer system interface (SCSI), comprising the steps of:

providing a plurality of flash memories for the auxiliary storage of the mass data;

selecting one of said flash memories, said selected one of said flash memories having a base address;

latching at least one address by incrementing the base address by a given value;

performing a desired data operation; and

releasing one of the flash memories by setting the base address to a predetermined value.

28. The method as claimed in claim 27, further comprising the step, after the selecting step, of latching a read command.

29. The method as claimed in claim 27, wherein said performing step comprises reading data of one page.

30. The method as claimed in claim 27, further comprising the step, after the selecting step, of latching a serial data input command by incrementing the base address by a given value.

31. The method as claimed in claim 27, wherein said performing step comprises writing data of one page.

32. The method as claimed in claim 27, further comprising the step, after the selecting step, of latching a program command by incrementing the base address by a given value, and then waiting.

33. The method as claimed in claim 27, further comprising the step, after the performing step, of latching a state read command by incrementing the base address by a given value, and then reading a state byte.

34. The method as claimed in claim 27, further comprising the step, after the selecting step, of latching a block erase setup command by incrementing the base address by a given value.

35. The method as claimed in claim 27, further comprising the step, after the latching step, of latching an erase command by incrementing the base address by a given value, wherein said performing step comprises performing a data erase operation.

36. The method as claimed in claim 27, further comprising the step, after the latching step, of latching a state read command by incrementing the base address by a given value, and reading a state byte.

47. The method as claimed in claim 27, further comprising the steps, between the providing and selecting steps, of:

providing a connector to provide a connection to the system via the SCSI;

providing a direct memory access (DMA) controller connected to said connector via an address bus, a control bus and a data bus, and connected to said flash memories via said data bus for controlling data access and transmission therebetween; and

providing a flash memory control circuit connected to said data bus, said address bus, said control bus and said flash memories for writing and reading data to and from the flash memories by page.

48. The method as claimed in claim 47, further comprising the step of providing a memory connected to said address bus, said control bus and said data bus for temporarily storing the data transferred between the connector and the flash memories.

49. The method as claimed in claim 47, further comprising the step of providing an address decoder connected to said address bus and to said control bus for decoding an address signal received through said address bus, and for transmitting decoded output signals to at least one of said connector and said flash memory control circuit.

50. The method as claimed in claim 49, wherein said flash memory control circuit comprises a decoder for decoding address signals, and for outputting decoded signals, said decoder being enabled in response to a selection signal provided by said address decoder.

51. The method as claimed in claim 50, said flash memory control circuit further comprising a flip-flop connected to said decoder for receiving an output signal therefrom, said flip-flop having an output for providing an address latch enable signal.

52. The method as claimed in claim 51, wherein said flip-flop has a clock input connected to said decoder for receiving an output signal therefrom.