Synchronous memory device utilizing request protocol and method of operation of same

• US 6,128,696 A
• Filed: 03/05/1999
• Issued: 10/03/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/263,225
• Time in Patent Office: 578 Days
• Field of Search: 713/400, 713/600, 710/3-5, 710/9-12, 710/36-39, 710/51, 710/61, 710/129-137, 711/100-105, 711/167-169, 365/189.01-189.05, 365/230.01-230.06, 365/233
• US Class Current: 711/105
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations. The method comprises receiving an external clock signal having a fixed frequency, receiving a read request, including addressing information, synchronously with respect to the external clock signal, initiating an internal memory addressing operation, in response to the read request, and outputting data onto the external bus synchronously with respect to the external clock signal. The synchronous memory device may include interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to an external clock. The write request packet may include N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M. The synchronous memory device may also include input receiver circuitry, coupled to the external bus, to receive data from the external bus synchronously with respect to the external clock wherein the received data is stored in the synchronous memory device in response to the write request packet.

Claims

1. A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations, the method comprising:

receiving an external clock signal having a fixed frequency;

receiving a read request packet, including addressing information, synchronously with respect to the external clock signal;

initiating an internal memory addressing operation, in response to the read request packet, wherein the internal memory addressing operation selects at least one memory location using the addressing information; and

outputting data from the at least one memory location onto the external bus synchronously with respect to the external clock signal.

2. The method of claim 1 wherein the read request packet is a packet including N bits of information, the external bus includes M number of signal lines, and N is substantially greater than M.

3. The method of claim 1 wherein the read request packet further includes control information and data information.

4. The method of claim 3 wherein the control information, address information and data information are time multiplexed over the external bus and wherein the read request packet is a packet including N bits of information, the external bus includes M number of signal lines, and N is substantially greater than M.

5. The method of claim 1 wherein the data is output onto the bus in accordance to a latency value stored in a register, the latency value being representative of a number of clock cycles of the external clock signal to transpire before driving data onto the bus.

6. The method of claim 1 further including automatically precharging the memory device after executing the read request packet.

7. The method of claim 6 wherein the read request packet includes control information, address information and data information which are time multiplexed over the external bus and wherein the read request packet is a packet including N bits of information, the external bus includes M number of signal lines, and N is substantially greater than M.

8. The method of claim 1 further including:

receiving device select information; and

comparing the device select information to a device identification value stored in a register on the memory device.

9. The method of claim 8 wherein the device select information and the read request packet are included in a packet.

10. The method of claim 9 wherein the device select information and the read request packet are included in the same packet.

11. The method of claim 1 further including receiving data transfer size information to define an amount of data to be transferred between an external bus and the memory device.

12. The method of claim 11 wherein the data transfer size information and the read request packet are included in a packet.

13. The method of claim 12 wherein the data transfer size information and the read request packet are included in the same packet.

14. A synchronous memory device having at least one memory section which includes a plurality of memory locations, the memory device comprises:

interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to a first external clock signal, wherein the write request packet includes N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M; and

input receiver circuitry, coupled to the external bus, to receive data from the external bus synchronously with respect to the first external clock signal wherein the data is stored in the at least one memory section in response to the write request packet.

15. The memory device of claim 14 further including:

a programmable register to store an identification value which identifies the memory device on the external bus;

comparison circuitry, coupled to the programmable register and the interface circuitry, to determine whether identification information in the write request packet corresponds to the identification value wherein, when the identification information corresponds to the identification value, the memory device responds to the write request packet.

16. The memory device of claim 14 wherein the write request packet includes control information, address information and data information, wherein the control, address and data information are time multiplexed over the external bus.

17. The memory device of claim 14 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal wherein the first external clock signal has a fixed frequency;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal using the first external clock; and

wherein the input receiver circuitry includes a plurality of input receivers, each coupled to the external bus, to sample data on the external bus in response to the internal clock signal and synchronously with respect to the first external clock signal.

18. The memory device of claim 17 wherein the internal clock generation circuitry includes a delay lock loop.

19. The memory device of claim 14 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal and a second external clock signal;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals using the first and second external clock signals; and

wherein the input receiver circuitry includes a plurality of input receivers, each coupled to the external bus, to sample data on the external bus in response to the first and second internal clock signals and synchronously with respect to the first and second external clock signals.

20. The memory device of claim 19 wherein the internal clock generation circuitry further includes a delay lock loop which generates the first internal clock signal.

21. The memory device of claim 19 wherein the internal clock generation circuitry further includes a first delay lock loop which generates the first internal clock signal and a second delay lock loop which generates the second internal clock signal.

22. The memory device of claim 14 further including a plurality of output drivers, coupled to the external bus, to output data onto the bus, in response to a read request packet, synchronously with respect to the first external clock signal.

23. The memory device of claim 22 wherein the interface circuitry receives the read request packet synchronously with respect to an external clock signal, wherein the read request packet includes P bits of information and P is substantially greater than M.

24. The memory device of claim 23 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal wherein the first external clock signal has a fixed frequency;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal using the first external clock signal; and

wherein the output drivers output data onto the external bus in response to the internal clock signal and synchronously with respect to the first external clock.

25. The memory device of claim 24 wherein the internal clock generation circuitry includes a delay lock loop.

26. The memory device of claim 23 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal and a second external clock signal;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals using the first and second external clock signals; and

wherein the output drivers output data onto the external bus in response to the first and second internal clock signals and synchronously with respect to the first and second external clock signals.

27. The memory device of claim 26 wherein the internal clock generation circuitry includes a delay lock loop which generates the first internal clock signal.

28. The memory device of claim 26 wherein the internal clock generation circuitry includes a first delay lock loop which generates the first internal clock signal and a second delay lock loop which generates the second internal clock signal.

29. A synchronous memory device having at least one memory section which includes a plurality of memory locations, the device comprises:

interface circuitry, coupled to an external bus, to receive a read request packet synchronously with respect to a first external clock signal, wherein the read request packet includes N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M; and

output driver circuitry, coupled to the external bus, to output data onto the external bus in response to the read request packet and synchronously with respect to the first external clock signal.

30. The memory device of claim 29 further including:

a programmable register to store an identification value which identifies the memory device;

comparison circuitry, coupled to the programmable register and the interface circuitry, to determine whether identification information in the read request packet corresponds to the identification value wherein when the identification information corresponds to the identification value, the memory device responds to the read request packet.

31. The memory device of claim 29 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal using the first external clock signal; and

wherein the output driver circuitry outputs data on the external bus in response to the internal clock signal.

32. The memory device of claim 31 wherein the internal clock generation circuitry includes a delay lock loop.

33. The memory device of claim 29 further including:

clock receiver circuitry, coupled to the external bus, to receive the first external clock signal and a second external clock signal;

internal clock generation circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals using the first and second external clock signals; and

wherein the output driver circuitry outputs data onto the external bus in response to the first and second internal clock signals.

34. The memory device of claim 33 wherein the internal clock generation circuitry includes a delay lock loop which generates the first internal clock signal.

35. The memory device of claim 33 wherein the internal clock generation circuitry includes a first delay lock loop which generates the first internal clock signal and a second delay lock loop which generates the second internal clock signal.

36. The memory system of claim 33 wherein the first and the second external clock signals are complementary.

37. A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations, the method comprising:

receiving an external clock signal having a fixed frequency;

receiving a write request packet, including addressing information, synchronously with respect to the external clock signal;

initiating an internal memory addressing operation, in response to the write request packet, wherein the internal memory addressing operation selects at least one memory location using the addressing information; and

inputting data from the external bus into the at least one memory location synchronously with respect to the external clock signal.

38. The method of claim 37 wherein the write request packet includes control information, address information and data information which are time multiplexed over the external bus and wherein the write request packet is a packet including N bits of information, the external bus includes M number of signal lines, and N is substantially greater than M.

39. The method of claim 37 further including:

receiving device select information; and

comparing the device select information to a device identification value stored in a register in the memory device.