Method for forming semiconductor device including a dual inlaid structure
First Claim
1. A method for forming a semiconductor device structure comprising the steps of:
- providing a semiconductor substrate;
forming a dielectric region over the semiconductor substrate;
forming a dual inlaid opening in the dielectric region, wherein;
the dual inlaid opening having an upper region having a first width between first substantially parallel first sidewall portions of the dual inlaid opening;
a lower region having a second width between second substantially parallel second sidewall portions of the dual inlaid opening; and
the upper region is significantly wider than the lower region; and
filling at least a portion of the dual inlaid opening with an oxygen-tolerant metal to form an inlaid portion having a top inlaid portion and a bottom inlaid portion.
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Abstract
A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced. Furthermore, the oxygen-tolerant material used to form the plugs (36a through 36c) herein prevents adverse plug oxidation which is present in the prior art during ferroelectric oxygen annealing.
83 Citations
32 Claims
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1. A method for forming a semiconductor device structure comprising the steps of:
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providing a semiconductor substrate; forming a dielectric region over the semiconductor substrate; forming a dual inlaid opening in the dielectric region, wherein; the dual inlaid opening having an upper region having a first width between first substantially parallel first sidewall portions of the dual inlaid opening; a lower region having a second width between second substantially parallel second sidewall portions of the dual inlaid opening; and the upper region is significantly wider than the lower region; and filling at least a portion of the dual inlaid opening with an oxygen-tolerant metal to form an inlaid portion having a top inlaid portion and a bottom inlaid portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 30)
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22. A method of forming a memory cell comprising the steps of:
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providing a semiconductor substrate; forming a transistor on the semiconductor substrate, the transistor having a first current electrode, a second current electrode, and a gate; forming a bit line coupled to the first current electrode; forming a word line coupled to the gate; forming a dual inlaid opening over the second current electrode; filling the dual inlaid opening with an oxygen-tolerant metal to form a first capacitor electrode at a top portion of the dual inlaid opening and a storage node portion at a bottom portion of the dual inlaid opening, the bottom portion being electrically coupled to the second current electrode; forming a dielectric region over the first capacitor electrode; and forming a second capacitor electrode over the dielectric region. - View Dependent Claims (23, 24, 25, 26, 27, 28, 31, 32)
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29. A method of forming a semiconductor structure, the method comprising the steps of:
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providing a semiconductor substrate; forming a memory cell transistor on the semiconductor substrate, the memory cell transistor having a first current electrode, a second current electrode, and a gate; forming a logic gate transistor on the semiconductor substrate, the logic gate transistor having a first current electrode, a second current electrode, and a gate; forming a bit line coupled to the first current electrode of the memory cell transistor; forming a word line coupled to the gate of the memory cell transistor; forming a dual inlaid opening over the second current electrode of the memory cell transistor; forming an inlaid opening over the second current electrode of the logic gate transistor; filling the dual inlaid opening and the inlaid opening with an oxygen-tolerant metal to form a first capacitor electrode electrically coupled to the second current electrode of the memory cell transistor and to form a contact plug electrically coupled to the second current electrode of the logic gate transistor; forming a dielectric region over the first capacitor electrode; and forming a second capacitor electrode over the dielectric region.
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Specification