Method for forming a BiCMOS integrated circuit with Nwell compensation implant and method

• US 6,130,122 A
• Filed: 07/15/1998
• Issued: 10/10/2000
• Est. Priority Date: 07/21/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Johnson, Frank Scott
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex A.
• Application Number:
  US09/115,857
• Time in Patent Office: 818 Days
• Field of Search: 438/202, 438/197, 438/207, 438/234, 438/204, 438/205, 438/236, 438/322, 438/326, 438/327, 438/340, 438/350, 438/919
• US Class Current: 438/202
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors

Abstract

A BiCMOS integrated circuit with Nwell compensation implants and a method for fabricating the same is disclosed. In accordance with the method of fabricating a BiCMOS integrated circuit, a plurality of Nwell regions are created in a semiconductor substrate. At least some of the Nwell regions comprise lightly doped collector regions of bipolar transistors while others of the Nwell regions comprise Nwell regions of MOS transistors. A plurality of isolation regions are created to electrically isolate at least some of the Nwell regions. A p-type dopant is implanted in at least some of the lightly doped collector regions of the bipolar transistors.

Claims

1. A method of fabricating a BiCMOS circuits, comprising the steps of:

forming a plurality of Nwell regions in a semiconductor substrate;

forming a plurality of isolation regions to electrically isolate at least some of the Nwell regions;

forming MOS transistors in a first subset of said plurality of Nwell regions;

forming extrinsic and intrinsic base regions of bipolar transistors in a second subset of Nwell regions; and

implanting a p-type dopant in at least some of said second subset of Nwell regions to form lightly doped collector regions in at least some of the bipolar transistors.

2. The method of claim 1, wherein the p-type dopant comprises Boron.

3. The method of claim 1, wherein said implanting a p-type dopant step comprises implanting said p-type dopant into at least some of the extrinsic and intrinsic base regions.

4. The method of claim 1, wherein said implanting a p-type dopant step comprises implanting said p-type dopant into at least some of the extrinsic base regions only.

5. The method of claim 1, wherein said step of forming MOS transistors forms a gate stack of the MOS transistors prior to the step of implanting the p-type dopant.

6. The method of claim 1, wherein said extrinsic and intrinsic base regions are formed prior to the step of implanting the p-type dopant.

7. The method of claim 1, further comprising the step of:

forming emitters of the bipolar transistors prior to said step of implanting the p-type dopant.

8. The method of claim 1, wherein the p-type dopant is implanted according to a first doping profile determined by the number of ions implanted and the energy used to implant them, the first doping profile comprising an approximately Gaussian distribution having a peak at a first depth, wherein the first depth is greater than a depth of the extrinsic base regions.

9. The method of claim 1, wherein the implanting step further comprises:

implanting a p-type dopant in at least some of the second subset of Nwell regions by implanting a first number of ions with a first energy; and

implanting a p-type dopant in the at least some of the second subset of Nwell regions by implanting a second number of ions with a second energy.

10. The method of claim 1, wherein the implanting step further comprises:

implanting a first p-type dopant in both the extrinsic and intrinsic base areas of at least some of the bipolar transistors;

wherein the method further comprises forming emitters of the bipolar transistors after the step of implanting a first p-type dopant and then implanting a second p-type dopant in the extrinsic base areas of at least some of the bipolar transistors.

11. The method of claim 10, wherein the first p-type dopant and the second p-type dopant comprise boron.

12. A method of fabricating a BiCMOS circuits, comprising the steps of:

forming a plurality of Pwell regions in a semiconductor substrate;

forming a plurality of isolation regions to electrically isolate at least some of the Pwell regions;

forming MOS transistors in a first subset of said plurality of Pwell regions;

forming extrinsic and intrinsic base regions of bipolar transistors in a second subset of Pwell regions; and

implanting a n-type dopant in at least some of said second subset of Pwell regions to form lightly doped collector regions in at least some of the bipolar transistors.