Method for making a complementary metal gate electrode technology

• US 6,130,123 A
• Filed: 06/30/1998
• Issued: 10/10/2000
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bai, Gang, Liang, Chunlin
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Thompson, Craig
• Application Number:
  US09/107,604
• Time in Patent Office: 833 Days
• Field of Search: 438/158, 438/712, 438/800, 438/217, 438/218, 438/197, 438/199, 148/DIG. 1
• US Class Current: 438/217
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

A method for making a circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

Claims

1. A method of forming a circuit device, comprising:

forming a gate dielectric overlying a region of a substrate;

depositing a metal layer over the gate dielectric; and

modifying the Fermi level of the metal layer.

2. The method of claim 1 further comprising patterning the metal layer into a gate electrode.

3. The method of claim 1, wherein modifying the Fermi level of the metal layer includes chemically reacting the metal layer with a compound.

4. The method of claim 3, wherein the region of the substrate includes a first region and a second region, and prior to modifying the first metal layer, the method further comprises:

masking the metal layer over the second region.

5. The method of claim 4, wherein the masking of the metal layer includes masking with an inert compound.

6. The method of claim 4, wherein the masking of the metal layer includes masking with a masking compound that reacts with the metal layer over the second region to modify the Fermi level of the reaction product.

7. The method of claim 6, wherein the masking compound is polysilicon.

8. The method of claim 1, wherein modifying the Fermi level of the metal layer includes alloying the metal layer with one of a second metal layer and a silicon.

9. The method of claim 8, wherein the region of the substrate includes a first region and a second region, and modifying the metal layer comprises modifying one of the first region and the second region.

10. The method of claim 9, wherein alloying the metal layer includes alloying with a polysilicon.

11. The method of claim 1, wherein modifying the Fermi level of the metal layer includes implanting an ion into the metal layer.

12. The method of claim 11, wherein the region of the substrate includes a first region and a second region, and modifying the metal layer comprises modifying one of the first region and the second region.

13. The method of claim 12, wherein after modifying the metal layer of one of the first region and the second region, the method comprises modifying the other of the first region and the second region.