Area array (flip chip) probe card

• US 6,130,546 A
• Filed: 05/11/1998
• Issued: 10/10/2000
• Est. Priority Date: 05/11/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Azizi, Sayed Kamallodin
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): TANG, MINH NHUT
• Application Number:
  US09/076,312
• Time in Patent Office: 883 Days
• Field of Search: 324/754, 324/761, 324/758, 324/757, 324/762, 324/755, 324/765, 324/72.5, 439/482
• US Class Current: 324/755.04
• CPC Class Codes: G01R 1/0416 Connectors, terminals G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735

Abstract

A method and apparatus for testing an integrated circuit die including a probe card (10) having a plurality of surface mount pads (45) arranged in a pattern (50) substantially corresponding to an area array pattern of die bumps (25) on the IC die. The pads and the die bumps are respectively electrically connected to each other with conductive probes (30). A plurality of test contacts (55) located around the periphery of the probe card (10) are in electrical contact to each surface mount pad (45) with electrical traces (65). An integrated circuit tester (60) having a plurality of test channels is electrically connected to a selected test contact (55) of the probe card (10), thereby forming a continuous conductive path between the integrated circuit tester (60) and the die bumps (25) on the IC die.

Claims

1. Apparatus for testing an integrated circuit (IC) die having a pattern of die bumps located thereon comprising:

a probe card having a probe card surface;

a plurality of surface mount pads on the probe card surface arranged in a pattern substantially corresponding to the pattern of die bumps on the IC die;

a plurality of electrical probes each having a top end and a bottom end;

said plurality of electrical probes arranged in a pattern substantially corresponding to the pattern of the die bumps to be tested, each probe corresponding to a selected die bump;

said plurality of electrical probes further arranged such that in use said top end is in mechanical and electrical contact with said surface mount pads on the probe card and said bottom end is in electrical contact with said die bumps on the IC die;

a means for holding the probes together in the pattern;

a plurality of test contacts located around the periphery of the probe card surface;

means for electrically connecting each surface mount pad with a corresponding test contact; and

an integrated circuit tester having a plurality of test channels, each test channel being electrically connected to a selected test contact of the probe card, thereby forming a continuous conductive path between the integrated circuit tester and the die bumps on the IC die.

2. The apparatus of claim 1 wherein the means for holding the plurality of probes comprises at least one guide plate.

3. The apparatus of claim 1 wherein each probe is individually collapsible in an axial direction.

4. The apparatus of claim 1 wherein the integrated circuit die bumps comprise controlled collapse chip connection (C4) bumps on a flip-chip integrated circuit die.

5. The apparatus of claim 4 wherein the integrated circuit die C4 bumps are arranged in an area array pattern.

6. The apparatus of claim 1 wherein the means for electrically connecting each surface mount pad with a corresponding test contact comprises a plurality of traces located on the probe card surface.

7. The apparatus of claim 1 wherein the means for electrically connecting each surface mount pad with a corresponding test contact comprises a plurality of jumper wires.

8. The apparatus of claim 1 wherein the number of die bumps is greater than 1000.

9. Apparatus for testing an integrated circuit die having a pattern of die bumps located thereon comprising:

a probe card having a plurality of surface mount pads arranged in a pattern substantially corresponding to the pattern of die bumps on the IC die, a plurality of test contacts located around the periphery of the probe card, and means for electrically connecting each surface mount pad with a corresponding test contact;

an integrated circuit tester having a plurality of test channels, each test channel being electrically connected to a selected test contact of the probe card;

a plurality of collapsible electrical probes arranged in a pattern substantially corresponding to the pattern of the die bumps, said collapsible probes being held compressibly between said plurality of surface mount pads and said corresponding pattern of die bumps, wherein a continuous conductive path between the integrated circuit tester and the die bumps is formed.

10. An apparatus for testing an integrated circuit die as in claim 9, wherein said plurality of collapsible electrical probes arranged in a pattern substantially corresponding to the pattern of the die bumps is maintained in said pattern by at least one non-conducting guide plate.

11. A method for testing an integrated circuit wafer having multiple integrated circuit (IC) dies formed therein, the IC dies having a pattern of die bumps located thereon, comprising the steps of:

(a) providing a probe card having a plurality of surface mount pads arranged in a pattern substantially corresponding to the pattern of die bumps on the IC die and a plurality of test contacts located around the periphery of the probe card;

(b) providing a plurality of electrical probes arranged in a pattern substantially corresponding to the pattern of the die bumps to be tested, each probe corresponding to a selected die bump and each probe having a top end and a bottom end;

(c) positioning the wafer near the probe card;

(d) engaging a plurality of probes with a first IC die on the wafer, the probes electrically and mechanically connecting to the surface mount pads and electrically connecting to selected ones of the die bumps, thereby forming a continuous conductive path between the test contacts and the die bumps;

(e) connecting at least one test channel of an integrated circuit tester having a plurality of test channels to a selected test contact of the probe card; and

(f) testing the integrated circuit die with the integrated circuit tester.

12. The method of claim 11 wherein the integrated circuit die bumps comprise controlled collapse chip connection (C4) bumps on a flip-chip integrated circuit die.

13. The method of claim 11 wherein the integrated circuit die C4 bumps are arranged in an area array pattern.

14. The method of claim 11 further comprising the steps of:

(g) disengaging the first IC die from the plurality of probes;

(h) re-positioning the wafer near the probe card;

(i) re-engaging the plurality of probes with a second IC die for testing; and

(j) testing the second IC die with the integrated circuit tester.