Synthesis-friendly FPGA architecture with variable length and variable timing interconnect

• US 6,130,551 A
• Filed: 01/19/1998
• Issued: 10/10/2000
• Est. Priority Date: 01/19/1998
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantis Corp (Lattice Semiconductor Corporation)
• Inventors: Agrawal, Om P., Nguyen, Bai, Sharpe-Geisler, Bradley A., Chang, Herman M., Tran, Giap H.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/008,762
• Time in Patent Office: 995 Days
• Field of Search: 326/41, 326/47, 326/39, 326/101
• US Class Current: 326/39
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.

Claims

1. A field programmable gate array device comprising:

(a) a first plurality P1 of repeated logic units wherein;

(a.1) each said logic unit is user-configurable to receive and process at least a second plurality P2 of input logic bits and to responsively produce result data having at least a third plurality P3 of output logic bits,

(a.2) said logic units are distributed among a plurality of horizontal rows, with each row of the plurality of rows having a fourth plurality P4 of said logic units;

(a.3) said logic units are further distributed among a plurality of vertical columns, with each column of the plurality of columns having a fifth plurality P5 of said logic units;

(a.4) said logic units include variable grain logic units (VG logic units) which are granulatable for implementing relatively coarse-grained functions of relatively high complexity from function spawning resources and for implementing with same function spawning resources, larger numbers of relatively finer-grained functions of relatively lower complexity but having independent input terms;

(b) a sixth plurality P6 of horizontal interconnect channels (HIC'"'"'s) correspondingly distributed adjacent to said horizontal rows of logic units, wherein;

(b.1) each said horizontal interconnect channel (HIC) includes at least P3 interconnect lines, and

(b.2) each said horizontal row of P4 logic units includes VG logic units that are each configurably couplable to a corresponding one of the P6 HIC'"'"'s at least for receiving input logic bits from the corresponding HIC or at least for outputting result data to the corresponding HIC; and

(c) switchbox areas distributed along the corresponding HIC of each said row of P4 logic units, wherein said switchbox areas include;

(c.1) braided switchboxes for twisting physical distribution of signals among at least some of said interconnect lines of the corresponding HIC so that rotated coupling options are provided by way of said configurable couplings between the P4 logic units and the corresponding HIC.

2. A field programmable gate array device according to claim 1 wherein:

(c.1a) each of P2 and P3 is an integer equal to or greater than 4 and;

(a.1a) each said logic unit is user-configurable to receive and process from adjacent interconnect lines of an adjacent HIC, at least said second plurality P2 of input logic bits and to responsively produce and output to the same HIC said result data having at least said third plurality P3 of output logic bits.

3. A field programmable gate array device according to claim 1 wherein:

(a.4) groups of said logic units are further wedged together such that each group of logic units defines a logic superstructure not having a HIC or vertical interconnect channel (VIC) passing therethrough and thereby spacing apart the logic units of said logic superstructure, wherein VIC'"'"'s are paired in immediate adjacency of one to another; and

(c.1c) groups of said switchbox areas, including at least one switchbox area having a braided switchbox, are also wedged together in adjacent VIC'"'"'s so as not to have other intervening structures spacing apart said wedged switchbox areas.

4. In a field programmable gate array device (FPGA) having a user-configurable interconnect network that includes a plurality of horizontal interconnect channels each with a diversified set of long-haul interconnect lines and shorter-haul interconnect lines, a switchbox areas subsystem comprising:

(a) a plurality of switchbox sub-areas each arranged within a horizontal interconnect channel (HIC) of the interconnect network and each including;

(a.1) at least one empty row and one non-empty row each of plural long-haul interconnect lines where the lines of the empty row are not substantially loaded by programmable interconnect points so that signals can propagate along the empty row more quickly than they can along the non-empty row,

wherein the empty row of one switchbox sub-areas continues to remain similarly empty in other switchbox sub-areas of the same HIC.

5. In an FPGA device having diversified interconnect resources including respective and orthogonally extending 2×

L, 4×

L and 8×

L buses with respective double-length lines, quad-length lines and octal-length lines, wherein each double-length line extends continuously adjacent to two variable grain blocks (VGB'"'"'s) which are granulatable for implementing relatively coarse-grained functions of relatively high complexity from function spawning resources and for implementing with same function spawning resources, larger numbers of relatively finer-grained functions of relatively lower complexity but having independent input terms,

a switchbox areas subsystem comprising;

first and second mirror symmetrical switchbox areas wherein said switchbox areas each include a braided switchbox at least at an intersection of two orthogonal 4×

L buses or 8×

L buses.

6. A method for use in an FPGA device having plural variable grain blocks (VGB'"'"'s), and diversified interconnect resources extending adjacent to said VGB'"'"'s, said diversified interconnect resources including respective and orthogonally extending 2×

L, 4×

L and 8×

L buses with respective double-length lines, quad-length lines and octal-length lines,

wherein each double-length line extends continuously adjacent to two VGB'"'"'s which are granulatable for implementing relatively coarse-grained functions of relatively high complexity from function spawning resources and for implementing with same function spawning resources, larger numbers of relatively finer-grained functions of relatively lower complexity but having independent input terms, said method comprising the steps of;

(a) sourcing a broadcast signal from a first VGB onto a longer line of the diversified interconnect resources of the FPGA device; and

(b) routing the sourced broadcast signal to an orthogonal and comparatively shorter line of the diversified interconnect resources for acquisition by a second VGB that is adjacent to said comparatively shorter line.

7. A synthesis-friendly, field programmable gate array (FPGA) device which can be programmably configured to implement logic constructs including Boolean logic constructs selected from a spectrum having relatively simple Boolean logic constructs of at least 1, 2 or 3 independent input terms to relatively more complex Boolean logic constructs of at least 4 independent input terms or more, said synthesis-friendly FPGA comprising:

(a) a regular set of programmably configurable and programmably granulatable logic blocks that can each implement, with use of function-spawning resources and when in a respective fine-grain mode, a plurality of relatively simple Boolean logic constructs of at least 3 independent input terms each, and that can further implement, with overlapping use of said function-spawning resources and when in a respective coarser-grain mode, a smaller number of relatively more complex Boolean logic constructs of at least 4 independent input terms each; and

(b) a first regular set of programmably selectable and diverse interconnect lines extending linearly in a first direction alongside said granulatable logic blocks for providing signal coupling between said granulatable logic blocks, the set of diverse interconnect lines including those of respective first, second and third continuous lengths in said first direction wherein;

(b.1) said first length spans a distance approximately equal to a corresponding side dimension of a coarsest of said granulatable logic blocks;

(b.2) said second length spans a distance that is at least as great as twice said first length but less than said third length; and

(b.3) said third length spans a distance that is at least as great as ten times said second length.

8. The synthesis-friendly, FPGA device of claim 7 and further wherein:

(b.2a) said second length spans a distance that is at least as great as four times said first length.

9. The synthesis-friendly, FPGA device of claim 7 and further wherein:

(b.3a) said third length spans a distance that is at least as great as 19 times said second length.

10. The synthesis-friendly, FPGA device of claim 7 and further comprising:

(c) a second regular set of programmably selectable and diverse interconnect lines extending linearly in a second direction that is orthogonal to the first direction, said second regular set of interconnect lines extending alongside said granulatable logic blocks for further providing signal coupling between said granulatable logic blocks, the second set of diverse interconnect lines also including those of respective first, second and third continuous lengths in said second direction.

11. The synthesis-friendly, FPGA device of claim 7 wherein said first regular set of programmably selectable and diverse interconnect lines further include those of respective fourth continuous length in said first direction where

(b.4) said fourth length spans a distance that is at least as great as twice said second length but less than said third length.

12. The synthesis-friendly, FPGA device of claim 7 and further comprising:

(c) direct connect lines each extending in orthogonal directions, each of said direct connect lines extending from a respective one of said granulatable logic blocks to others of the granulatable logic blocks for further providing signal coupling between said one and the others of the granulatable logic blocks.

13. The synthesis-friendly, FPGA device of claim 7 and further wherein RC time constants of respective ones of said second length lines are each at least about 4 times less than respective RC time constants of corresponding ones of said third length lines.

14. The synthesis-friendly, FPGA device of claim 7 and further wherein RC time constants of respective ones of said first length lines are each at least about 3 times less than respective RC time constants of corresponding ones of said second length lines.

15. The synthesis-friendly, FPGA device of claim 7 and further comprising:

(c) braided switchboxes for twisting physical distribution of signals among at least some of said interconnect lines so that rotated coupling options are provided by way of configurable couplings between the granulatable logic units and the correspondingly braided lines.

16. The synthesis-friendly, FPGA device of claim 7 and further comprising:

(c) a plurality of input/output blocks (IOB'"'"'s) for transferring input or result signals between external devices and said FPGA device, wherein the plural IOB'"'"'s are organized to transfer bus-wide signals to and from said third length lines.

17. The synthesis-friendly, FPGA device of claim 16 wherein:

(c.1) each IOB has at least two selectable and different paths by way of which the IOB can transfer signals to and from said third length lines.

18. The synthesis-friendly, FPGA device of claim 16 and further comprising:

(d) a plurality of memory blocks further organized to transfer bus-wide signals to and from said third length lines.

19. The synthesis-friendly, FPGA device of claim 18 wherein said memory blocks have at least two independent access ports, a first of the access ports being coupled to said third length lines, and a second of the access ports being coupled to said second length lines.

20. The synthesis-friendly, FPGA device of claim 7 wherein said device is a monolithic chip having at least 4 layers of metal interconnect and further wherein:

(b.3a) said third length lines are defined by metal conductors extending through at least one of said metal interconnect layers.

21. The synthesis-friendly, FPGA device of claim 7 and further comprising:

(c) feedback lines each extending adjacent to a respective subset of said granulatable logic blocks for further providing localized signal coupling between said subset of granulatable logic blocks, where each feedback line has an RC time constant that is less than a corresponding RC time constant of a corresponding first length line.

22. The synthesis-friendly, FPGA device of claim 7 and further wherein said complex ones of the Boolean logic constructs can have at least 16 independent input terms.

23. The synthesis-friendly, FPGA device of claim 22 wherein said third length lines are organized into plural buses with at least 16 third length lines in each bus so that said at least 16 independent input terms can be simultaneously carried by each bus for coupling into respective inputs of said granulatable logic blocks.

24. The synthesis-friendly, FPGA device of claim 23 wherein a linear succession of granulatable logic blocks can supply at least 16 independent output signals to a commonly adjacent one of said plural buses.

25. The synthesis-friendly, FPGA device of claim 7 and further wherein said complex ones of the Boolean logic constructs can have 32 independent input terms.

26. A synthesis-friendly, field programmable gate array (FPGA) device which may be programmably configured to implement logic constructs including Boolean logic constructs selected from a spectrum having relatively simple Boolean logic constructs of at least 1, 2 or 3 independent input terms to relatively more complex Boolean logic constructs of at least 4 independent input terms or more, said synthesis-friendly FPGA comprising:

(a) a regular set of programmably configurable and programmably granulatable logic blocks that can each implement, with use of function-spawning resources and when in a respective fine-grain mode, a plurality of relatively simple Boolean logic constructs of at least 3 independent input terms each, and that can further implement, with overlapping use of said function-spawning resources and when in a respective coarser-grain mode, a smaller number of relatively more complex Boolean logic constructs of at least 4 independent input terms each; and

(b) a set of programmably selectable and diverse interconnect lines for providing signal coupling between said granulatable logic blocks, the set of diverse interconnect lines including those of respective and comparative small, intermediate and largest continuous lengths wherein;

(b.1) said small length spans a distance approximately equal to a corresponding dimension of a coarsest of said granulatable logic blocks;

(b.2) said intermediate length spans a distance that is approximately greater than twice said small length; and

(b.3) said largest length spans a distance that is greater than said intermediate length.