Circuit configuration for producing negative voltages, charge pump having at least two circuit configurations and method of operating a charge pump

• US 6,130,574 A
• Filed: 07/26/1999
• Issued: 10/10/2000
• Est. Priority Date: 01/24/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Lauterbach, Christl, Bloch, Martin
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/360,946
• Time in Patent Office: 442 Days
• Field of Search: 327/536, 327/537, 327/564, 327/565, 327/566
• US Class Current: 327/536
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters

Abstract

A circuit configuration for producing negative voltages includes a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection. A second transistor has a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor. A second capacitor has a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection. The transistors are MOS transistors produced in a triple well. A third transistor has a first connection connected to the second connection of the first transistor, a second connection connected to the well(s) containing the transistors and a gate connection connected to the first connection of the first transistor. A charge pump having at least two of the circuit configurations and a method of operating the charge pump are also provided.

Claims

1. A circuit configuration for producing negative voltages, comprising;

an input connection and an output connection;

first and second clock signal connections;

a first MOS transistor having a first connection connected to said input connection, a second connection connected to said output connection, and a gate connection;

a first capacitor connected between said gate connection of said first transistor and said first clock signal connection;

a second MOS transistor having a first connection connected to said gate connection of said first transistor, a second connection connected to said second connection of said first transistor, and a gate connection connected to said first connection of said first transistor;

a second capacitor having a first connection connected to said second connection of said first transistor and a second connection connected to said second clock signal connection;

a third transistor having a first connection connected to said second connection of said first transistor, a second connection connected to backgates of said first and second transistors, and a gate connection connected to said first connection of said first transistor;

a third capacitor having a first connection connected to said first connection of said first transistor and a second connection connected to backgates of said first and second transistors; and

said first, second and third MOS transistors produced in a triple well structure.

2. A charge pump for generating negative voltages, comprising:

at least two circuit configurations connected in series, said circuit configurations including a first circuit configuration, and each of said circuit configurations including;

an input connection and an output connection;

first and second clock signal connections;

a first MOS transistor having a first connection connected to said input connection, a second connection connected to said output connection, and a gate connection;

a first capacitor connected between said gate connection of said first transistor and said first clock signal connection;

a second MOS transistor having a first connection connected to said gate connection of said first transistor, a second connection connected to said second connection of said first transistor, and a gate connection connected to said first connection of said first transistor;

a second capacitor having a first connection connected to said second connection of said first transistor and a second connection connected to said second clock signal connection;

a third transistor having a first connection connected to said second connection of said first transistor, a second connection connected to backgates of said first and second transistors, and a gate connection connected to said first connection of said first transistor;

a third capacitor having a first connection connected to said first connection of said first transistor and a second connection connected to backgates of said first and second transistors; and

said first, second and third MOS transistors produced in a triple well structure; and

said input connection of said first circuit configuration connected to ground potential.

3. A charge pump according to claim 2,

wherein the circuit is operated by shifting clock signals at said clock signal connections of a respective one of said circuit configurations by half a clock period of clock signals of a preceding one of said circuit configurations.

4. A charge pump according to claim 3, wherein a duty ratio of at least clock signals at said second clock signal connections is greater than 0.5.