Digitally self-calibrating current-mode D/A converter

• US 6,130,632 A
• Filed: 04/16/1998
• Issued: 10/10/2000
• Est. Priority Date: 04/16/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Opris, Ion E.
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): KOST, JASON L
• Application Number:
  US09/062,157
• Time in Patent Office: 908 Days
• Field of Search: 341/120, 341/121, 341/144
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.

Claims

1. An apparatus including a current cell for a digitally self-calibrating current-mode digital-to- analog converter, comprising:

a reference signal generator configured to provide a reference signal;

a signal output terminal;

a signal comparison terminal;

a reference terminal;

a first conversion switch coupled between said signal generator and said signal output terminal;

a second conversion switch coupled between said signal generator and said reference terminal; and

a calibration switch coupled between said signal generator and said signal comparison terminal;

wherein said first conversion switch, said second conversion switch and said calibration switch selectively couple said signal generator to at least one of said signal output terminal, said signal comparison terminal and said reference terminal, and in accordance thereto, provide an output signal.

2. The apparatus of claim 1 wherein said reference terminal is ground.

3. The apparatus of claim 1 further including a controller coupled to said first conversion switch, said second conversion switch, and said calibration switch, said controller configured to receive an input signal and in accordance thereto, generate one or more control signals.

4. The apparatus of claim 3 wherein said first conversion switch, said second conversion switch, and said calibration switch selectively couple said reference signal generator, said signal output terminal, said signal comparison terminal, and said reference terminal in accordance with said control signal.

5. The apparatus of claim 1 wherein during a first state, said signal generator is configured to couple to said signal comparison terminal, and further, during a second state, said signal generator is configured to couple to one of said reference terminal and said signal output terminal.

6. The apparatus of claim 5 wherein said first state is a calibration stage of said current cell and further, wherein said second state is a conversion stage of said current cell.

7. An apparatus including a digitally self-calibrating current mode digital-to-analog converter, comprising:

an encoder configured to receive an input signal and in accordance thereto generate an encoded signal;

an output terminal;

an output switch coupled to said output terminal;

a calibration switch;

a reference signal switch coupled to said calibration switch and said output switch;

a reference signal generator coupled to said reference signal switch configured to generate a reference signal;

a calibration engine coupled to said encoder configured to generate a plurality of correction coefficients;

a plurality of current cells each coupled to said calibration engine, each of said current cells configured to receive said plurality of correction coefficients and in accordance thereto, generate a first and second current cell signals;

a comparator having a first input terminal, a second input terminal and a comparator output terminal, said first input terminal coupled to said calibration switch, said second input terminal coupled to said plurality of current cells, and said comparator output terminal coupled to said calibration engine, said comparator configured to receive said first and second current cell signals and to selectively receive said reference signal and in accordance thereto provide a comparator output signal to said calibration engine; and

a controller coupled to said encoder, said reference signal switch, said calibration switch, said output switch and said calibration engine, configured to generate one or more control signals;

wherein said comparator receives said reference signal in accordance with the switching of said calibration switch and said reference signal switch, and in accordance with generate a compared signal; and

further

wherein said output switch selectively provides an output signal to said output terminal in accordance with said one or more control signals.

8. The apparatus of claim 7 wherein said encoder is configured to receive and to store said correction coefficients from said calibration engine.

9. The apparatus of claim 8 wherein said encoder includes a memory having a plurality of memory locations for storing said correction coefficients.

10. The apparatus of claim 7 wherein said calibration engine is configured to provide a calibration signal to said plurality of current cells in accordance with said one or more control signals from said controller.

11. An apparatus including a current mode comparator for a digitally self-calibrating current mode digital-to-analog converter, comprising:

a first input terminal configured to receive a first input signal;

a second input terminal configured to receive a second input signal;

an output terminal configured to provide an output signal, said output terminal coupled to said second input terminal;

a reference terminal;

a first transistor having a first terminal, a second terminal and a third terminal, said third terminal coupled to said reference terminal;

a second transistor having a first terminal, a second terminal and a third terminal, said third terminal coupled to said reference terminal and said second transistor second terminal coupled to said first transistor second terminal; and

a plurality of switches coupled between said first input terminal, said second input terminal and said first and second transistor first terminals;

wherein said plurality of switches selectively couple said first and second input terminals to said first and second transistor first terminals and in accordance thereto providing a comparator output signal to said output terminal such that the current density of said first and second transistors are substantially constant.

12. The apparatus of claim 11 wherein said reference terminal is a ground terminal.

13. The apparatus of claim 11 wherein said first and second transistors are MOS transistors.

14. The apparatus of claim 13 wherein said first and second transistors first terminals are drain terminals, said first and second transistors second terminals are gate terminals, and further, wherein said first and second transistors third terminals are source terminals.

15. The apparatus of claim 11 further including a buffer coupled between said output terminal and said second input terminal configured to amplify said output signal.

16. The apparatus of claim 11 further including a controller configured to provide comparator control signals to said plurality of switches, wherein said plurality of switches includes:

a first pair of switches configured to couple said first and second input terminals to said first and second transistors respectively, in accordance with a first comparator control signal; and

a second pair of switches configured to couple said same first and second input terminals to said first and second transistors respectively, in accordance with a second comparator control signal.

17. The apparatus of claim 16 wherein said first and second comparator control signals are non- overlapping.

18. A method of digitally self-calibrating a current mode digital-to-analog converter including a plurality of current cells, said method comprising the steps of:

initializing a plurality of memory locations with an initialization factor;

calibrating each of a plurality of current cells with a first calibration factor and in accordance thereto generating a plurality of correction coefficients, each of said correction coefficients corresponding to one of said current cells;

calibrating said correction coefficients in accordance with a second calibration factor and storing each of said calibrated correction coefficients in said respective memory locations; and

normalizing said plurality of calibrated correction coefficients in accordance with a normalization factor and in accordance thereto generating an output signal.

19. The method of claim 18 wherein said initialization factor is 1, wherein said first calibration factor includes a first reference signal, and further, wherein said second calibration factor includes a second reference signal.

20. The method of claim 18 wherein said memory locations include a random access memory.

21. A method of performing digital correction for a current mode digital-to-analog converter including N current cells where N is an integer, said method comprising the steps of:

for each i^th current cell, where i=1 to N;

receiving an input digital signal;

comparing said input digital signal to a corresponding i^th correction coefficient;

if said input digital signal is larger than said corresponding i^th correction coefficient, generating a first output digital signal and subtracting said i^th correction coefficient from said input digital signal to generate an input digital signal for (i+1)^th current cell; and

if said input digital signal is not larger than said corresponding i^th correction coefficient, generating a second output digital signal.

22. The method of claim 21 wherein said first output digital signal is 1 and wherein said second output digital signal is 0.

23. The method of claim 21 further including the step of storing said N output digital signals.