Method and apparatus for a reduced instruction set architecture for multidimensional image processing

• US 6,130,967 A
• Filed: 07/03/1997
• Issued: 10/10/2000
• Est. Priority Date: 07/03/1997
• Status: Expired due to Term

• Current Assignee: Tripath Imaging Incorporated (Becton Dickinson & Co)
• Original Assignee: Tripath Imaging Incorporated (Becton Dickinson & Co)
• Inventors: Hayenga, Jon W., Lee, Shih-Jong J.
• Primary Examiner(s): BELLA, MATTHEW C
• Application Number:
  US08/888,120
• Time in Patent Office: 1,195 Days
• Field of Search: 382/128, 382/302, 382/304, 382/307, 395/800.1, 395/800.11, 395/800.16, 395/800.33, 345/505, 709/251, 710/100, 708/7
• US Class Current: 382/302
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A reduced instruction set architecture implements complicated image processing algorithms that are decomposed into combinations of simple operations. The simple operations are further decomposed into multiple operations of one dimensional data with an address controller to scan data in a highly flexible fashion for multi-dimensional applications.

Claims

1. An image processing apparatus comprising:

(a) a host computer;

(b) a plurality of field of view processors;

(c) a system bus to connect the computer and the plurality of field of view processors;

(d) an image disk interface connected to the system bus;

(e) a means for acquiring an image connected to an image interface and image reformatter wherein the image interface is also connected to the system bus; and

(f) a high speed image bus ring for connecting the plurality of field of view processors via the image interface and the image disk interface wherein the field of view processors perform multidimensional image processing, and wherein one of the field of view processors further comprises;

(i) a first multiplier for multiplying a first image input signal by a first coefficient;

(ii) a second multiplier for multiplying a second coefficient by a second image input signal;

(iii) a third multiplier for multiplying a first constant by the first image input signal;

(iv) a fourth multiplier for multiplying a second constant by the second image input signal; and

(v) a first summer for summing the output of a first multiplier and a second multiplier and a first constant and a second summer for summing the output of the third multiplier and the fourth multiplier and a second constant.

2. The apparatus of claim 1 further comprising means for filtering and image transformation wherein the means for filtering and image transformation performs a coefficient controlled operation.

3. The apparatus of claim 2 wherein the pixel processing unit comprises a mask and thresholded image pixel processor having filter processing and transform processing.

4. The apparatus of claim 1 further comprising an iterative delay operation filter.

5. The apparatus of claim 1 further comprising an iterative delay addition filter.

6. The apparatus of claim 1 further comprising an iterative delay subtraction filter.

7. The apparatus of claim 1 further comprising an iterative delay maximum filter.

8. The apparatus of claim 1 further comprising an iterative uniform filter.

9. The apparatus of claim 1 wherein each one of the field of view processing modules comprises a plurality of pixel processing units connected through a cross point interconnective multiplexer to a plurality of image buffer memories.

10. The apparatus of claim 1 wherein a translation operation is implemented when the first coefficient is 1, the second coefficient is 0, the third coefficient is 0 and the fourth coefficient is 1, where the first constant is 0 and the second constant is 0.

11. The apparatus of claim 1 wherein the scaling operation is performed when the first coefficient is set to the scaling factor, the second coefficient is set to 0, the third coefficient is set to 0 and the fourth coefficient is set to the scaling factor.

12. The apparatus of claim 1 wherein a horizontal flip operation is performed and the first coefficient is -1, the second coefficient is 0, the third coefficient is 0 and the fourth coefficient is 1, the first constant is the total amount of columns in the input image and the second constant is 0.

13. The apparatus of claim 1 wherein a vertical flip operation is performed when the first coefficient is 1, the second coefficient is 0, the third coefficient is 0, the fourth coefficient is -1, the first constant is 0 and the second constant is the total number of rows of the input image.

14. The apparatus of claim 1 where a transpose function is performed when the first coefficient is 0, the second coefficient is 1, the third coefficient is 1, the fourth coefficient is 0, the first constant is 0 and the second constant is 0.

15. The apparatus of claim 1 wherein a horizontal skew operation is performed when the first coefficient is 1, the second coefficient is -tangent of theta, where theta is the skew angle, the third coefficient is 0, the fourth coefficient is 1, the first constant is 0 and the second constant is 0.

16. The apparatus of claim 1 wherein a vertical skew operation is performed when the first coefficient is 1, the second coefficient is 0, the third coefficient is -tangent of the vertical skew angle, the fourth coefficient is 1, the first constant is 0 and the second constant is 0.

17. The apparatus of claim 1 wherein a rotation operation is performed when the first coefficient is the cosine of the rotation angle, the second coefficient is the sine of the rotation angle, and the third coefficient is -sine of the rotation angle, the fourth coefficient is the cosine of the rotation angle, the first constant is 0 and the second constant is 0.