Plug-and-play data cable with protocol translation

• US 6,131,125 A
• Filed: 11/14/1997
• Issued: 10/10/2000
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Lsi Usa Inc.
• Inventors: Silverman, Joel, Rostoker, Michael D.
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US08/970,992
• Time in Patent Office: 1,061 Days
• Field of Search: 395/500, 439/76.1, 710/71, 710/65, 710/70, 710/72, 710/63, 709/250, 709/230, 709/227
• US Class Current: 709/250
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent "plug-and-play" capabilities.

Claims

1. A protocol translation cable assembly comprising:

a first connector having a first plurality of pins;

a second connector having a second plurality of pins;

an electrical cable coupling said first connector to said second connector, said electrical cable including a plurality of conductors; and

translation circuitry coupled to at least some of said plurality of conductors of said electrical cable at points between ends of said first plurality of pins of said first connector and ends of said second plurality of pins of said second connector, said translation circuitry deriving its power from said electrical cable, said translation circuitry including a first protocol processor communicating with said first connector and a second protocol processor communicating with said second connector, said first protocol processor and said second protocol processor being coupled together for mutual communication, such that said first protocol processor is capable of communicating with a first apparatus via said first connector with said first protocol and such that said second protocol processor is capable of communicating with a second apparatus via said second connector with said second protocol;

wherein each of said first and said second protocol is selected from the group consisting of a USB, an Ethernet, a Fire wire, a SCSI, a modem, a wireless, a video, a printer, and a serial protocols.

2. A protocol translation cable as recited in claim 1, wherein said first protocol is a USB protocol, and wherein said second protocol is an Ethernet protocol.

3. A protocol translation cable assembly comprising:

a first connector having a first plurality of pins;

a second connector having a second plurality of pins;

an electrical cable coupling said first connector to said second connector, said electrical cable including a plurality of conductors; and

translation circuitry coupled to at least some of said plurality of conductors of said electrical cable at points between ends of said first plurality of pins of said first connector and ends of said second plurality of pins of said second connector, said translation circuitry deriving its power from said electrical cable, said translation circuitry including a first protocol processor communicating with said first connector and a second protocol processor communicating with said second connector, said first protocol processor and said second protocol processor being coupled together for mutual communication, such that said first protocol processor is capable of first communicating with a first apparatus via said first connector with said first protocol and such that said second protocol processor is capable of communicating with a second apparatus via said second connector with said second protocol, said first protocol being different from said second protocol.

4. A protocol translation cable as recited in claim 3 wherein said translation circuitry further includes memory coupled to at least one of said first protocol processor and said second protocol processor.

5. A protocol translation cable as recited in claim 4 wherein said first protocol is implemented with a first driver stored in said memory, and wherein said second protocol is implemented with a second driver stored in said memory.

6. A protocol translation cable as recited in claim 5, wherein said memory is a read-only memory including a collection of drivers, and wherein said at least one of said first protocol processor and said second protocol processor determines an appropriate driver for at least one of said first driver and said second driver selected from said collection of drivers.

7. A protocol translation cable as recited in claim 6, wherein said at least one of said first protocol processor and said second protocol processor determines said appropriate driver by an analysis of electrical signals present upon said plurality of pins of at least corresponding one of said first connector and said second connector.

8. A protocol translation cable as recited in claim 5, wherein said memory is a read/write memory including a collection of drivers, and wherein said at least one of said first protocol processor and said second protocol processor determines an appropriate driver for at least one of said first driver and said second driver selected from said collection of drivers.

9. A protocol translation cable as recited in claim 8, wherein said at least one of said first protocol processor and said second protocol processor determines said appropriate driver by an analysis of electrical signals present upon said plurality of pins of at least corresponding one of said first connector and said second connector.

10. A protocol translation cable as recited in claim 5, wherein said memory is a read/write memory, and wherein at least one of said first driver and said second driver are loaded into said read/write memory through at least one of said first connector and said second connector.

11. A protocol translation cable as recited in claim 3 wherein said first protocol is a first fixed protocol and wherein said second protocol is a second fixed protocol.

12. A single chip protocol translator comprising:

a unitary semiconductor substrate integrating translation circuitry including a first protocol processor and a second protocol processor, said first protocol processor and said second protocol processor being coupled together for mutual communication, such that said first protocol processor is capable of communicating with first external devices with a first protocol and such that said second protocol processor is capable of communicating with second external devices with a second protocol, said first protocol being different from said second protocol;

wherein said translation circuitry includes memory coupled to at least one of said first protocol processor and second protocol processor, and wherein said first protocol is implemented with a first driver stored in said memory and said second protocol is implemented with a second driver stored in said memory.

13. A single chip protocol translator as recited in claim 12, wherein said memory stores a collection of drivers, and wherein said at least one of said first protocol processor and said second protocol processor selects an appropriate driver for at least one of said first driver and said second driver selected from said collection of drivers.

14. A single chip protocol translator as recited in claim 12, wherein at least one of said first driver and said second driver is loaded into said memory from at least one of said first external devices and said second external devices.

15. A method for plug-and-play compatibility between a first apparatus capable of digitally communicating with a first protocol through a first apparatus connector and a second apparatus capable of digitally communicating with a second protocol through a second apparatus connector, said method comprising:

determining a first communication protocol received at a first apparatus connector;

enabling a first protocol driver appropriate to said determined first protocol in a first protocol processor;

determining a second communication protocol received at a second apparatus connector;

enabling a second protocol driver appropriate to said determined second protocol in a second protocol processor;

translating digital communications provided at said first apparatus connector in said first protocol into digital communications at said second apparatus connector in said second protocol through said first protocol processor and then said second protocol processor; and

translating digital communications provided at said second apparatus connector in second protocol into digital communications at said first apparatus connector in said first protocol through said second protocol processor and then said first protocol processor.

16. A method for plug-and-play compatibility as recited in claim 15, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in a memory coupled to said first protocol processor.

17. A method for plug-and-play compatibility as recited in claim 15, wherein enabling said first protocol driver includes downloading said first protocol driver through said first apparatus connector to a memory coupled to said first protocol processor.

18. A method for plug-and-play compatibility of a protocol translation circuitry, said method comprising:

determining a first communication protocol received at a first group of terminals of said protocol translation circuitry;

enabling a first protocol driver appropriate to said determined first protocol in a first protocol processor within said protocol translation circuitry;

determining a second communication protocol received at a second group of terminals of said protocol translation circuitry;

enabling a second protocol driver appropriate to said determined second protocol in a second protocol processor within said protocol translation circuitry;

translating digital communications in said first protocol provided at said first group of terminals into digital communications in said second protocol at said second group of terminals through said first protocol processor and then said second protocol processor; and

translating digital communications in said second protocol provided at said second group of terminals into digital communications in said first protocol at said first group of terminals through said second protocol processor and then said first protocol processor.

19. A method for plug-and-play compatibility as recited in claim 18, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in memory coupled to said first protocol processor.

20. A method for plug-and-play compatibility as recited in claim 18, wherein enabling said first protocol driver includes downloading said first protocol driver through said first group of terminals to memory coupled to said first protocol processor.

21. A protocol translation circuitry for plug-and-play capability, comprising:

a first group of terminals for receiving first digital communications in a first protocol;

a second group of terminals for receiving second digital communications in a second protocol;

a first protocol processor coupled to said first group of terminals; and

a second protocol processor coupled to said second group of terminals, wherein said first protocol processor determines said first protocol received at said first group of terminals and enables in said first protocol processor a first driver appropriate to said determined first protocol, and said second protocol processor determines said second protocol received at said second group of terminals and enables in said second protocol processor a second driver appropriate to said determined second protocol,

wherein said first digital communications provided at said first group of terminals in said first protocol are translated through said first protocol processor and then said second protocol processor into translated first digital communications in said second protocol at said second group of terminals, and said second digital communications received at said second group of terminals in said second protocol are translated through said second protocol processor and then said first protocol processor into translated second digital communications in said first protocol at said first group of terminals.

22. A protocol translation circuitry as recited in claim 21, further comprising memory coupled to said first protocol processor, wherein said memory stores a collection of protocol drivers, and said first protocol processor selects said first protocol driver from said collection of protocol drivers.

23. A protocol translation circuitry as recited in claim 21, further comprising a memory coupled to said first protocol processor, wherein said first protocol driver is loaded through said first group of terminals into said memory.

24. A cable assembly for plug-and-play capability between a first apparatuscapable of digitally communicating with a first protocol through a first apparatus connector and a second apparatus capable of digitally communicating with a second protocol through a second apparatus connector, said cable assembly comprising:

a first cable connector adapted to be coupled to said first apparatus connector;

a second cable connector adapted to be coupled to said second apparatus connector;

an electrical cable coupling said first cable connector to said second cable connector, said electrical cable including a plurality of conductors;

a translation circuitry for translating digital communications provided at said first apparatus connector in said first protocol into digital communications at said second apparatus connector in said second protocol, and for translating digital communications provided at said second apparatus connector in said second protocol into digital communications at said first apparatus connector in said first protocol; and

wherein said translation circuitry determines said first protocol and said second protocol, and enables a first protocol driver appropriate to said determined first protocol and a second protocol driver appropriate to said determined second protocol in said translation circuitry.

25. A cable assembly as recited in claim 24, wherein said translation circuitry includes memory that stores a collection of protocol drivers, and said translation circuitry selects at least one of said first protocol driver and said second protocol driver from said collection of protocol drivers.

26. A cable assembly as recited in claim 24, wherein said translation circuitry includes memory, and at least one of said first protocol driver and said second protocol driver is loaded through at least one of said first cable connector and said second cable connector into said memory.

27. A protocol translator for plug-and-play capability, comprising:

a first group of terminals for receiving first digital communications in a first protocol;

a second group of terminals for receiving second digital communications in a second protocol; and

a translation circuitry provided between said first group of terminals and said second group of terminals, wherein said translation circuitry determines said first protocol received at said first group of terminals and said second protocol received at said second group of terminals, and enables a first protocol driver appropriate to said determined first protocol and a second protocol driver appropriate to said determined second protocol in said translation circuitry, such that said translation circuitry translates said first digital communications in said first protocol provided at said first group of terminals into translated first digital communications in said second protocol at said second group of terminals, and also translates said second digital communications in said second protocol provided at said second group of terminals into translated second digital communications in said first protocol at said second group of terminals.

28. A protocol translator as recited in claim 27, further comprising memory coupled to said translation circuitry, wherein said memory stores a collection of protocol drivers, and said translation circuitry selects at least one of said first protocol driver and said second protocol driver from said collection of protocol drivers.

29. A protocol translator as recited in 27, further comprising memory coupled to said translation circuitry, wherein at least one of said first protocol driver and said second protocol driver is loaded through at least one of said first group of terminals and said second group of terminals into said memory.

30. A method for plug-and-play compatibility of a protocol translation circuitry, said method comprising:

determining a first communication protocol received at a first group of terminals of said protocol translation circuitry;

enabling a first protocol driver appropriate to said determined first protocol in said protocol translation circuitry;

determining a second communication protocol received at a second group of terminals of said protocol translation circuitry;

enabling a second protocol driver appropriate to said determined second protocol in said protocol translation circuitry;

translating digital communications in said first protocol provided at said first group of terminals into digital communications in said second protocol at said second group of terminals through said translation circuitry; and

translating digital communications in said second protocol provided at said second group of terminals into digital communications in said first protocol at said first group of terminals through said translation circuitry.

31. A method for plug-and-play compatibility as recited in claim 30, wherein enabling said first protocol driver includes selecting said first protocol driver from a collection of drivers stored in memory coupled to said translation circuitry.

32. A method for plug-and-play compatibility as recited in claim 30, wherein enabling said first protocol driver includes downloading said first protocol driver through said first group of terminals to a read/write memory coupled to said translation circuitry.

33. A system comprising:

a first apparatus capable of digitally communicating with a first protocol through a first apparatus connector;

a second apparatus capable of digitally communicating with a second protocol through a second apparatus connector; and

a cable assembly connecting said first apparatus to said second apparatus, said cable including;

a first connector having a first plurality of pins;

a second connector having a second plurality of pins;

an electrical cable coupling said first connector to said second connector, said electrical cable including a plurality of conductors; and

translation circuitry coupled to at least some of said plurality of conductors of said electrical cable at points between ends of said first plurality of pins of said first connector and ends of said second plurality of pins of said second connector, said translation circuitry deriving its power from said electrical cable, said translation circuitry including a first protocol processor communicating with said first connector and a second protocol processor communicating with said second connector, said first protocol processor and said second protocol processor being coupled together for mutual communication, such that said first protocol processor is capable of first communicating with a first apparatus via said first connector with said first protocol and such that said second protocol processor is capable of communicating with a second apparatus via said second connector with said second protocol, said first protocol being different from said second protocol.