Computer system including an enhanced communication interface for an ACPI-compliant controller

• US 6,131,131 A
• Filed: 01/22/1998
• Issued: 10/10/2000
• Est. Priority Date: 01/22/1998
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Bassman, Robert, Rao, Anil
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US09/012,434
• Time in Patent Office: 992 Days
• Field of Search: 710/1, 710/15, 710/33, 710/52, 710/57
• US Class Current: 710/15
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A conventional keyboard-style ACPI interface is greatly enhanced by the inclusion of a bi-directional hardware buffer and a special software protocol that allows multiple byte command and data messages to be sent in a burst fashion. The illustrative enhanced ACPI interface alleviates congestion in data transmission that results from the overhead incurred by transferring messages using multiple interrupts per message. An extended embedded controller includes a buffer for temporary storage of a plurality of data bytes and a program code for controlling data transfers to and from the buffer using a data handling technique that is ACPI-compliant.

Claims

1. A computer system comprising:

a processor;

a host bus coupled to the processor;

an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic that is capable of controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte;

a local bus coupled to the embedded controller;

a device coupled to the embedded controller via the local bus;

an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer; and

an extended control logic coupled to the embedded controller, the extended control logic capable of controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit,

the processor being capable of loading data into the multiple-byte buffer, sending a transaction command to the extended control logic, and waiting for the commanded transaction to complete, the extended control logic controlling execution of the transaction.

2. A computer system according to claim 1 wherein:

the control logic and the extended control logic control data byte transfer operate in compliance with an Advanced Configuration and Power Interface (ACPI) specification.

6. A computer system according to claim 1 further comprising:

an embedded controller process executable in the embedded controller and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the embedded controller process further including;

an interrupt service routine responsive to a command written to a standard command register;

a read status register process for determining whether the data transfer is a standard-ACPI data transfer control process or an enhanced-ACPI data transfer control process;

a read command register process for determining a data transfer operation requested by the processor; and

an interrupt request process responsive to a determination that the data transfer is a standard-ACPI data transfer control process for generating an interrupt request directed to the processor.

9. A computer system according to claim 1 wherein:

the control logic is a programmed machine code implementation in firmware.

10. A computer system according to claim 1 wherein:

the control logic is a programmable machine code implementation in a modifiable storage.

11. A computer system according to claim 1 wherein:

the control logic is a circuit implementation.

12. A computer system according to claim 1 wherein:

the enhanced control logic is a programmed machine code implementation in firmware.

13. A computer system according to claim 1 wherein:

the enhanced control logic is a programmable machine code implementation in a modifiable storage.

14. A computer system according to claim 1 wherein:

the enhanced control logic is a circuit implementation.

15. A computer program product comprising:

a computer usable medium having computable readable code embodied therein including the control logic and the enhanced control logic according to claim 1.

3. A computer system comprising:

a processor;

a host bus coupled to the processor;

an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte;

a local bus coupled to the embedded controller;

a device coupled to the embedded controller via the local bus;

an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer;

an extended control logic coupled to the embedded controller, the extended control logic controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit;

a host process executable in the processor and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the host process further including;

a process for writing a data packet including a plurality of data bytes to the multiple-byte buffer for an enhanced-ACPI data transfer;

an ACPI-compliant process for writing a command code to a standard command register;

a sleep process for temporarily terminating execution awaiting a wakeup signal;

a read/write data byte process responsive in the standard-ACPI data transfer control process to an interrupt request for reading/writing data from/to a data register in response to a wakeup signal;

a read response status process responsive in the enhanced-ACPI data transfer mode to an interrupt request for reading a response status from a data register;

a read response data process responsive in the enhanced-ACPI data transfer mode for reading a response data packet from the multiple-byte buffer; and

a process completion process responsive in the enhanced-ACPI data transfer mode and generating a single interrupt at completion of an enhanced-ACPI data transfer mode command.

4. A computer system according to claim 3 wherein:

the read/write data byte process is responsive to either deassertion of an input buffer full bit or and interrupt request signal.

5. A computer system according to claim 3 further comprising:

a standard-ACPI mode sleep process alternating with the read/write data byte process and repeating each byte and resulting in an interrupt per byte.

7. A computer system comprising:

a processor;

a host bus coupled to the processor;

an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte;

a local bus coupled to the embedded controller;

a device coupled to the embedded controller via the local bus;

an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer;

an extended control logic coupled to the embedded controller, the extended control logic controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit;

an embedded controller process executable in the embedded controller and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the embedded controller process further including;

an interrupt service routine responsive to a command written to a standard command register;

a read status register process for determining whether the data transfer is a standard-ACPI data transfer control process or an enhanced-ACPI data transfer control process;

a read command register process for determining a data transfer operation requested by the processor;

an interrupt request process responsive to a determination that the data transfer is a standard-ACPI data transfer control process for generating an interrupt request directed to the processor;

a read buffer length process responsive to a determination that the data transfer is an enhanced-ACPI data transfer control process for reading a buffer length from the multiple-byte buffer;

a read data packet process responsive in the enhanced-ACPI data transfer control process for reading a data packet from the multiple-byte buffer;

a processing process responsive to the read data packet process for executing the received enhanced-ACPI command;

a write response data packet process responsive to the processing process for writing result data from executing the received enhanced-ACPI command to the multiple-byte buffer;

a write response status byte responsive to the write response data packet process for writing a response status to a data register; and

an interrupt request process responsive to the write response status byte process for generating an interrupt request directed to the processor.

8. A computer system comprising:

a processor;

a host bus coupled to the processor;

an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte;

a local bus coupled to the embedded controller;

a device consoled to the embedded controller via the local bus;

an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer;

an extended control logic coupled to the embedded controller, the extended control logic controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit;

an embedded controller process executable in the embedded controller and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the embedded controller process further including;

an interrupt service routine responsive to a command written to a standard command register;

a read status register process for determining whether the data transfer is a standard-ACPI data transfer control process or an enhanced-ACPI data transfer control process;

a read command register process for determining a data transfer operation requested by the processor;

a read buffer length process responsive to a determination that the data transfer is an enhanced-ACPI data transfer control process for reading a buffer length from the multiple-byte buffer;

a read data packet process responsive in the enhanced-ACPI data transfer control process for reading a data packet from the multiple-byte buffer;

a processing process responsive to the read data packet process for executing the received enhanced-ACPI command;

a write response data packet process responsive to the processing process for writing result data from executing the received enhanced-ACPI command to the multiple-byte buffer;

a write response status byte responsive to the write response data packet process for writing a response status to a data register; and

an interrupt request process responsive to the write response status byte process for generating an interrupt request directed to the processor.

16. An interface in a computer system including a processor and a device coupled to the processor via a host bus and a local bus comprising:

an embedded controller connectable to the processor via the host bus and connectable to the device via the local bus;

an enhanced interface coupled to the embedded controller via the local bus, connectable to the processor via the host bus, and connectable to the device via the local bus, the enhanced interface including a multiple-byte buffer; and

a control logic coupled to the embedded controller including;

a first logic for transferring commands, messages, and data between the processor and the device in a byte-by-byte transfer, each byte being transferred in conjunction with an interrupt; and

a second logic for transferring multiple bytes of the commands, messages, and data between the processor and the device via the multiple-byte buffer so that multiple bytes are transferred per interrupt, the processor being capable of loading data into the multiple-byte buffer, sending a transaction command to the control logic, and waiting for the commanded transaction to complete, the control logic controlling execution of the transaction.

17. An interface according to claim 16 wherein:

the first logic transfers the commands, messages, and data according to an Advanced Configuration and Power Interface (ACPI) specification; and

the second logic transfers multiple bytes using an ACPI-compliant transfer technique.

18. An interface according to claim 16 wherein the enhanced interface further comprises:

a first unidirectional multiple-byte buffer for transferring commands, messages, and data from the processor to the device; and

a second unidirectional multiple-byte buffer for transferring commands, messages, and data from the device to the processor.

19. An interface according to claim 18 wherein the enhanced interface further comprises:

a control register; and

a status register.

20. A method of transferring data within a computer system including a processor, a host bus coupled to the processor, an embedded controller coupled to the processor via the host bus and including a buffer and a control logic, a local bus coupled to the embedded controller, a device coupled to the embedded controller via the local bus, and an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer, the method comprising:

controlling transfer of data bytes via the buffer byte-by-byte;

monitoring a buffer full bit at the transfer of each byte;

controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit, including;

loading data into the multiple-byte buffer;

sending a transaction command to the control logic; and

waiting for the commanded transaction to complete, the control logic controlling execution of the transaction.

21. A method according to claim 20 wherein:

the data byte transfer is in compliance with an Advanced Configuration and Power Interface (ACPI) specification.

22. A computer program for execution on a computer system including a processor, a host bus coupled to the processor, an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte, a local bus coupled to the embedded controller, a device coupled to the embedded controller via the local bus, an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer, and an extended control logic coupled to the embedded controller, the extended control logic controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit, the computer program implementing a host process executable in the processor and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the computer program comprising:

a process for writing a data packet including a plurality of data bytes to the multiple-byte buffer for an enhanced-ACPI data transfer;

an ACPI-compliant process for writing a command code to a standard command register;

a sleep process for temporarily terminating execution awaiting a wakeup signal;

a read/write data byte process responsive in the standard-ACPI data transfer control process to an interrupt request for reading/writing data from/to a data register in response to a wakeup signal;

a read response status process responsive in the enhanced-ACPI data transfer mode to an interrupt request for reading a response status from a data register;

a read response data process responsive in the enhanced-ACPI data transfer mode for reading a response data packet from the multiple-byte buffer; and

a process completion process responsive in the enhanced-ACPI data transfer mode and generating a single interrupt at completion of a enhanced-ACPI data transfer mode command.

23. A computer program product comprising:

a computer usable medium having computable readable code embodied therein including the computer program according to claim 22.

24. A computer program for execution on a computer system including a processor, a host bus coupled to the processor, an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte, a local bus coupled to the embedded controller, a device coupled to the embedded controller via the local bus, an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer, an extended control logic coupled to the embedded controller, the extended control logic controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit, and an embedded controller process executable in the embedded controller, the computer program implementing a combined standard-ACPI and enhanced-ACPI data transfer control process comprising:

an interrupt service routine responsive to a command written to a standard command register;

a read status register process for determining whether the data transfer is a standard-ACPI data transfer control process or an enhanced-ACPI data transfer control process;

a read command register process for determining a data transfer operation requested by the processor;

an interrupt request process responsive to a determination that the data transfer is a standard-ACPI data transfer control process for generating an interrupt request directed to the processor;

a read buffer length process responsive to a determination that the data transfer is an enhanced-ACPI data transfer control process for reading a buffer length from the multiple-byte buffer;

a read data packet process responsive in the enhanced-ACPI data transfer control process for reading a data packet from the multiple-byte buffer;

a processing process responsive to the read data packet process for executing the received enhanced-ACPI command;

a write response data packet process responsive to the processing process for writing result data from executing the received enhanced-ACPI command to the multiple-byte buffer;

a write response status byte responsive to the write response data packet process for writing a response status to a data register; and

an interrupt request process responsive to the write response status byte process for generating an interrupt request directed to the processor.

25. A computer program product comprising:

a computer usable medium having computable readable code embodied therein including the computer program according to claim 24.

26. A computer program for execution on a computer system including a processor, a host bus coupled to the processor, an embedded controller coupled to the processor via the host bus, the embedded controller including a buffer and control logic controlling transfer data bytes via the buffer byte-by-byte and monitoring a buffer full bit at the transfer of each byte, a local bus coupled to the embedded controller, a device coupled to the embedded controller via the local bus, an extended interface coupled to the processor via the host bus and coupled to the device and the embedded controller via the local bus, the extended interface including a multiple-byte buffer, an extended control logic coupled to the embedded controller, the extended control logic capable of controlling the embedded controller and the extended interface to transfer a plurality of data bytes for a single monitoring of the buffer full bit, the computer program implementing an embedded controller process executable in the embedded controller and including a combined standard-ACPI and enhanced-ACPI data transfer control process, the computer program comprising:

an interrupt service routine responsive to a command written to a standard command register;

a read status register process for determining whether the data transfer is a standard-ACPI data transfer control process or an enhanced-ACPI data transfer control process;

a read command register process for determining a data transfer operation requested by the processor;

a read buffer length process responsive to a determination that the data transfer is an enhanced-ACPI data transfer control process for reading a buffer length from the multiple-byte buffer;

a read data packet process responsive in the enhanced-ACPI data transfer control process for reading a data packet from the multiple-byte buffer;

a processing process responsive to the read data packet process for executing the received enhanced-ACPI command;

a write response data packet process responsive to the processing process for writing result data from executing the received enhanced-ACPI command to the multiple-byte buffer;

a write response status byte responsive to the write response data packet process for writing a response status to a data register; and

an interrupt request process responsive to the write response status byte process for generating an interrupt request directed to the processor.

27. A computer program product comprising:

a computer usable medium having computable readable code embodied therein including the computer program according to claim 26.