System for downloading programs

• US 6,131,159 A
• Filed: 05/08/1992
• Issued: 10/10/2000
• Est. Priority Date: 05/08/1992
• Status: Expired due to Fees

• Current Assignee: Rembrandt Technologies, LP (Rembrandt IP Management, LLC)
• Original Assignee: Paradyne Corporation (Dasan Networks Incorporated)
• Inventors: Hecht, Gideon, Snoll, Donald C., Holmquist, Kurt Ervin
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US07/880,257
• Time in Patent Office: 3,077 Days
• Field of Search: 395/700, 395/651, 395/652, 395/653, 395/712, 364/DIG. 1, 364/DIG. 2, 713/1, 713/2, 713/100, 711/114, 711/1, 711/145, 711/202-206, 710/23, 710/104
• US Class Current: 713/1
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A modified version of the operating communication program of a stored program controlled apparatus is installed with the aid of a downloadable start address specification means, optionally realized with an EEPROM memory. The start address specification means stores information that is downloaded through a communication port in the apparatus, and that information is used in defining the address from where the communication programs are initiated. In accordance with the method of this invention, downloading of the entire new set of programs is effected by first downloading a segment of the essential portion of the new package of programs. Control is then transferred to the new segment by downloading appropriate information into the start address specification means. Thereafter, utilizing the downloaded essential portion of the new package of programs, the remainder of the new package is downloaded.

Claims

1. A system comprising:

(a) a processor;

(b) a memory, and a set of programs stored in said memory that are executed when the system needs to be initialized, said memory being of a type which may be completely updated in its entirety but which is not volatile, said memory being the only program memory in said system; and

(c) alterable storage means for holding a displacement multi-bit memory address that is used to point to the starting address accessed by the processor when initializing.

2. The system of claim 1 wherein said memory is an EEPROM memory.

3. The system of claim 1 wherein said memory consists of 2-FLASH EEPROM devices.

4. The system of claim 1 wherein said alterable storage means is an EEPROM memory.

5. The system of claim 1 further comprising translation means interposed between said alterable storage means and said memory, wherein said alterable storage means holds an address that translates between addresses directed to the memory via said translation means and addresses actually applied to the memory by said translation means.

6. A system comprising:

(a) a processor;

(b) a memory coupled to said processor, said memory being the only program memory in the system, said memory being completely updatable in its entirety but non-volatile, there being a set of programs stored in said memory that are executed when the system needs to be initialized; and

(c) alterable memory means for storing a multi-bit memory address that controls the starting address accessed by the processor when initializing.

7. The system of claim 6 further comprising means for receiving a trigger signal at a telecommunications input port of the system to begin execution of said programs.

8. A system comprising;

(a) a processor;

(b) a memory and a communications port coupled to said processor, said communications port being adapted to communicate with devices which are external to said system, said memory being completely updatable in its entirety but non-volatile;

(c) a program module in said memory that, when activated by said processor, effects communication with said port; and

(d) operationally alterable means for setting the starting address of said program, which address is supplied to said system via said communication port.

9. The system of claim 8 wherein:

(a) said memory contains a first set of programs and a second set of programs;

(b) said memory is at least twice the size of the size of the first set of programs; and

(c) said operationally alterable means sets the starting position of the program executed by said processor in connection with communication with said port at a second specified location that is M removed from the first location, M being half the size of said memory.

10. A system comprising:

(a) a processor;

(b) a communication port coupled to said processor, said communication port being adapted to communicate with devices which are external to said system;

(c) a memory coupled to said processor, said memory being non-volatile and capable of being completely updated in its entirety, said memory containing programs, including a set of programs that are executed when the system needs to be initialized and a program for controlling communication through said communication port; and

(d) means for activating said program for controlling communication and receiving information through said communication port to modify the programs in said memory, said information including the program for controlling communication through said communication port and a command that is executed by said processor effectively when it is received.

11. The system of claim 10 wherein the communication port is a telecommunication port.

12. The system of claim 10 wherein the communication port is a telecommunication port and the programs execute the functions of a modem.

13. The system of claim 10 where the communication port receives commands to be executed by the processor and data to be stored in the memory.

14. The system of claim 10 wherein said means for receiving includes means for altering the program according to the information obtained by the means for receiving.

15. The system of claim 10 wherein said means for receiving modifies the programs by altering a portion of the memory contents pursuant to data received via said communication port.

16. The system of claim 10 wherein said means for receiving modifies the programs by replacing them with program data received via said communication port.

17. The system of claim 10 where the means for altering alters all of the programs in the system in a single communication session with said communication port.

18. A system comprising:

(a) a processor;

(b) a memory coupled to said processor, said memory being of a type, which is completely updatable in its entirety but non-volatile;

(c) a set of program means stored in said memory that are activated when said system needs to be updated wit a new set of programs, and

(d) alterable storage means for holding an offset memory address that is used to point to a starting address accessed by said processor when initializing.

19. The system of claim 18 wherein said memory is an EEPROM memory.

20. The system of claim 18 wherein said memory consists of 2 FLASH EEPROM devices.

21. The system of claim 18 wherein said alterable storage means is an EEPROM memory.