Integrated micromechanical sensor device and process for producing it

• US 6,133,059 A
• Filed: 02/25/1998
• Issued: 10/17/2000
• Est. Priority Date: 09/21/1993
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Werner, Wolfgang
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US09/030,229
• Time in Patent Office: 965 Days
• Field of Search: 438/50, 438/52, 73/514.29, 73/514.32, 73/514.21, 73/514.22, 73/514.23
• US Class Current: 438/52
• CPC Class Codes: B81B 3/0013 Structures dimensioned for mechanical prevention of stiction, e.g. spring with increased stiffness
• CPC Class Codes: B81C 1/00928 Eliminating or avoiding remaining moisture after the wet etch release of the movable structure
• CPC Class Codes: B81C 2201/117 Using supercritical fluid, e.g. carbon dioxide, for removing sacrificial layers
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type

Abstract

The integrated micromechanical sensor device contains a body with a substrate (1) on which an insulating layer (2) and thereon a monocrystalline silicon layer (3) are arranged, in which the silicon layer has trenches as far as the surface of the insulating layer, and the side walls of the trenches as well as the side of the silicon layer adjacent to the insulating layer have a first doping type (n⁺) and the silicon layer has a second doping type (n^-) at least in a partial region of its remaining surface, in which the silicon layer has a transistor arrangement in a first region (TB) and a sensor arrangement in a second region (SB), for which the insulating layer (2) is partly removed under the second region. Such a sensor device has considerable advantages over known devices with regard to its properties and its production process.

Claims

1. A process for producing an integrated micromechanical sensor device, which comprises:

a) forming a body with an insulating layer disposed on a substrate, and a monocrystalline silicon layer disposed on the insulating layer, the silicon layer being of a doping type;

b) etching trenches with trench walls into the silicon layer and to a surface of the insulating layer;

c) doping the trench walls;

d) producing a transistor configuration in a first region of the silicon layer; and

e) removing the insulating layer below a second region of the silicon layer.

2. The process according to claim 1, which further comprises doping the silicon layer with a first doping type on a side thereof adjacent the insulating layer, and doping the silicon layer with a second doping type on an opposite side thereof.

3. The process according to claim 1, which further comprises filling the trenches with a doping insulant subsequently to step a), and exposing the trenches at the second second region prior to step e).

4. The process according to claim 1, which further comprises filling the trenches with phosphorus glass subsequently to step a) and exposing the trenches at the second region prior to step e).

5. The process according to claim 1, wherein step c) comprises doping the trench walls in correspondence with the doping type of the silicon layer.

6. The process according to claim 1, wherein step d) comprises producing the transistor configuration according to one of bipolar, MOS or bipolar/MOS standard process.

7. The process according to claim 1, which further comprises, subsequently to step d), removing a passivation layer in a sensor region, and subsequently removing the insulant from the trenches of the sensor region and the insulating layer below the silicon layer.