Multi-chip module employing carrier substrate with micromachined alignment structures and method of forming

• US 6,133,065 A
• Filed: 01/16/1998
• Issued: 10/17/2000
• Est. Priority Date: 03/06/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US09/008,678
• Time in Patent Office: 1,005 Days
• Field of Search: 438/39, 438/164, 438/108, 438/107, 438/412, 438/455, 438/598, 438/687, 438/106, 438/612, 257/685, 257/170, 257/667, 257/777, 257/780, 257/737, 257/738, 257/778, 257/786, 257/686, 257/623
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, "semiconductor elements") may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond. The present invention also includes a stacked configuration. After attachment of semiconductor elements, the carrier substrates can be stacked to form a high density stacked configuration.

Claims

1. A method for producing a semiconductor carrier substrate, comprising:

providing a carrier substrate having a layer of semiconductor material with a substantially planar surface;

forming at least one elongated mesa of semiconductor material defined by sidewalls extending upwardly to a top from at least one substrate plane of semiconductor material below said at least one elongated mesa by selectively removing material from said substantially planar surface of said layer of semiconductor material to a depth less than a thickness of the layer of semiconductor material;

substantially simultaneously forming an insulating layer over said at least one substrate plane and said top and sidewalls of said at least one elongated mesa; and

forming conductive traces on said insulating layer including mutually laterally spaced, substantially linear conductive trace segments oriented transversely to said at least one elongated mesa, said mutually laterally spaced, substantially linear conductive trace segments of said conductive traces each extending over at least one of said sidewalls of said at least one elongated mesa and onto said at least one substrate plane.

2. The method of claim 1, further including selecting said carrier substrate from a group consisting of monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

3. The method of claim 1, wherein forming said at least one elongated mesa comprises:

forming a mask layer over said substantially planar surface of said layer of semiconductor material;

removing a portion of said mask layer to expose areas of said substantially planar surface of said layer of semiconductor material; and

etching said exposed substantially planar surface areas of said layer of substrate material to form said at least one elongated mesa and said at least one substrate plane.

4. The method of claim 3, further including forming said mask layer at least partially of silicon nitride.

5. The method of claim 3, wherein the etching said exposed substantially planar surface areas of said layer of semiconductor material includes performing a wet anisotropic etch.

6. The method of claim 1, further including forming said insulating layer of silicon dioxide.

7. The method of claim 1, further including forming said conductive traces of at least copper.

8. The method of claim 1, wherein the forming said conductive traces comprises:

depositing a conductive material layer on said insulating layer; and

selectively removing portions of said conductive material layer.

9. The method of claim 8, further including forming said conductive traces of at least copper.

10. The method of claim 9, wherein the forming said conductive traces further includes:

depositing a layer of chrome on said insulating layer;

depositing a layer of copper/chrome alloy on said chrome layer; and

depositing a layer of copper on said copper/chrome alloy layer.

11. The method of claim 1, wherein the forming said conductive traces comprises depositing a conductive paste on said insulating layer by silk screening.

12. The method of claim 1, wherein the forming said conductive traces comprises extruding a conductive paste on said insulating layer.

13. The method of claim 1, wherein the forming said conductive traces comprises:

depositing a second insulating layer on said insulating layer;

etching through said second insulating layer to form a trough; and

filling said trough with a conductive material.

14. The method of claim 1, further including:

applying a passivation layer over said insulating layer and said conductive traces; and

selectively removing portions of said passivation layer to expose contact areas on the conductive traces.

15. A method for producing a semiconductor device, comprising the steps of:

providing a carrier substrate including a layer of material exhibiting a face surface;

performing at least one elongated mesa with sidewalls extending upwardly to a top from at least one base substrate plane below said at least one elongated mesa by removing said layer of material from said face surface to a depth less than a thickness of said layer of material;

substantially simultaneously forming an insulating layer extending over said top and sidewalls of said at least one elongated mesa and said at least one base substrate plane;

forming a plurality of elongated conductive traces on said insulating layer including mutually laterally spaced, substantially linear conductive trace segments oriented transversely to said at least one elongated mesa, said mutually laterally spaced, substantially linear conductive trace segments of said plurality of elongated conductive traces each extends over at least a portion of one of said sidewalls and over a portion of said at least one base substrate plane adjacent said one of said sidewalls;

providing at least one semiconductor element having at least one conductive connector protruding therefrom; and

forming an electrical connection between said at least one semiconductor element and said at least one of said plurality of elongated conductive traces through said at least one conductive connector by contacting a first area of said at least one of said plurality of elongated conductive trace on said at least a portion of one of said sidewalls and a second area of said at least one of said plurality of elongated conductive trace extending over said adjacent portion of at least one base substrate plane.

16. The method of claim 15, further comprising selecting said carrier substrate from a group consisting of monocrystalline silicon, silicon-on-glass, silicon-on-sapphire, germanium, and ceramic.

17. The method of claim 15, wherein forming said at least one elongated mesa comprises:

forming a mask layer over said face surface of said material layer;

removing a portion of said mask layer to expose areas of said face surface of said material layer; and

etching said exposed face surface areas to form said at least one elongated mesa and said at least one base substrate plane.

18. The method of claim 17, further comprising forming said mask layer at least partially from silicon nitride.

19. The method of claim 17, wherein the etching said exposed face surface areas includes performing a wet anisotropic etch.

20. The method of claim 15, further comprising forming said insulating layer at least partially from silicon dioxide.

21. The method of claim 15, further comprising forming said plurality of elongated conductive traces at least partially from copper.

22. The method of claim 15, wherein the forming said plurality of elongated conductive traces comprises:

depositing a conductive material layer on said insulating layer; and

selectively removing portions of said conductive material layer.

23. The method of claim 22, further comprising forming said plurality of elongated conductive traces at least partially from copper.

24. The method of claim 23, wherein the forming said plurality of elongated conductive traces further includes:

depositing a layer of chrome on said insulating layer;

depositing a layer of copper/chrome alloy on said chrome layer; and

depositing a layer of copper on said copper/chrome alloy layer.

25. The method of claim 15, wherein the forming said plurality of elongated conductive traces comprises depositing a conductive paste on said insulating layer by silk screening.

26. The method of claim 15, wherein the forming said plurality of elongated conductive traces comprises extruding a conductive paste on said insulating layer.

27. The method of claim 15, wherein the forming said plurality of elongated conductive traces comprises:

depositing a second insulating layer on said insulating layer;

etching through said second insulating layer to form a trough; and

filling said trough with a conductive material.

28. The method of claim 15, further including:

applying a passivation layer over said insulating layer and said plurality of elongated conductive traces; and

selectively removing portions of said passivation layer to expose contact areas on the plurality of elongated conductive traces.

29. The method of claim 15, further comprising forming said at least one semiconductor element as a semiconductor chip.

30. The method of claim 15, further comprising forming each of said carrier substrate and said at least one semiconductor element from an entire silicon wafer.

31. The method of claim 15, wherein said at least one conductive connector comprises a plurality of conductive connectors, wherein said plurality of elongated conductive traces each extends over at least a portion of one of said sidewalls and over an adjacent portion of said at least one base substrate plane and further comprising forming a plurality of electrical connections between said at least one semiconductor element and said plurality of elongated conductive traces through said plurality of conductive connectors by contacting each of said plurality of elongated conductive traces with at least one conductive connector at a first area of a conductive trace on said at least a portion of one of said sidewalls and a second area of said at least one of said plurality of elongated conductive traces extending over said adjacent portion of at least one base substrate plane.

32. The method of claim 15, wherein the forming said at least one elongated mesa comprises forming at least two adjacent elongated mesas, and further comprising forming at least one elongated conductive trace extending over at least a portion of one of said elongated mesa sidewalls of a first elongated mesa, over an adjacent portion of said at least one base substrate plane, and over at least a portion of an elongated mesa sidewall of a second, adjacent elongated mesa, and causing said at least one conductive connector to electrically contact said at least one of said plurality of elongated conductive trace on a first area of said at least one of said plurality of elongated conductive trace over said at least a portion said one of said elongated mesa sidewalls of said first elongated mesa, on a second area of said at least one of said plurality of elongated conductive traces over said at least one base substrate plane, and on a third area of said at least one elongated conductive trace over said at least a portion of said elongated mesa sidewall of said second, adjacent elongated mesa.

33. The method of claim 15, further comprising forming said at least one conductive connector as a ball of reflowable material.

34. The method of claim 33, further comprising forming said reflowable material as a lead/tin alloy.