Methods and apparatuses for binning partially completed integrated circuits based upon test results

• US 6,133,582 A
• Filed: 05/14/1998
• Issued: 10/17/2000
• Est. Priority Date: 05/14/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Lightspeed Semiconductor Corporation
• Inventors: Osann, Robert Jr., Eltoukhy, Shafy
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US09/079,016
• Time in Patent Office: 887 Days
• Field of Search: 257/48, 257/202, 257/758, 257/203, 257/208, 257/210, 257/211, 257/797, 324/769, 324/765, 438/11
• US Class Current: 257/48
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and electrical testing circuits are located in the active chip area and/or in the scribe line area between dies on the wafer. Performance and/or electrical tests are performed after generic fabrication is completed, but before the final customization of the wafers. Wafers are sorted and assigned to performance and/or yield bins based upon the results of the performance and/or electrical tests. The contents of different bins are provided to different customers for addition of the final N application specific metal interconnection layers based upon the customer'"'"'s performance and/or yield requirements. In another embodiment, all M layers are deposited prior to performance and/or electrical testing; however, the Mth layer is not etched within the active die area prior to performance and/or electrical testing. Subsequent to binning based upon the test results, the final customization is performed by etching the Mth metal layer. Further, a programmable gate array integrated circuit which has features for testing and binning for speed and performance grading prior to final personalization or programming on the top layer or layers of interconnecting material is provided.

Claims

1. An integrated circuit wafer, comprising:

a plurality of generic gate array dies, each die including an untestable generic gate array circuit, each circuit including M-N generically-patterned metal interconnection layers, wherein the generic gate array circuits are not yet electrically operative and are capable of receiving N application-specific custom metal interconnection layers; and

a self-contained performance testing circuit having probe pads on the (M-N)th metal interconnection layer, wherein the performance testing circuit is accessible through the probe pads and is electrically functional.

2. An integrated circuit wafer as in claim 1,

wherein the self-contained performance testing circuit comprises a series of buffers having an input and an output.

3. An integrated circuit wafer as in claim 1, wherein the self-contained performance testing circuit comprises a ring oscillator having an output.

4. An integrated circuit wafer as in claim 1, wherein the self-contained performance testing circuit is located in a scribe line area between the plurality of generic gate array dies.

5. An integrated circuit wafer as in claim 1, wherein the self-contained performance testing circuit is located within an active area of the generic gate array dies.

6. An integrated circuit wafer as in claim 1, wherein M is four, and N is one.

7. An integrated circuit wafer, comprising:

a plurality of generic gate array dies, each die including an untestable generic gate array circuit, each circuit including M-1 generically-patterned metal interconnection layers and an Mth unpatterned metal interconnection layer, wherein each generic gate array circuit is not yet electrically operative; and

a self-contained performance testing circuit having probe pads on the Mth metal interconnection layer, wherein the self-contained performance testing circuit is accessible through the probe pads and is electrically functional.

8. An integrated circuit wafer as in claim 7,

wherein the self-contained performance testing circuit comprises a series of buffers having an input and an output.

9. An integrated circuit wafer as in claim 7, wherein the self-contained performance testing circuit comprises a ring oscillator having an output.

10. An integrated circuit wafer as in claim 7, wherein the self-contained performance testing circuit is located in a scribe line area between the plurality of generic gate array dies.

11. An integrated circuit wafer as in claim 7, wherein the self-contained performance testing circuit is located within an active area of the generic gate array dies.

12. An integrated circuit wafer as in claim 7, wherein M is four.

13. An integrated circuit wafer, comprising:

a plurality of generic gate array dies, each die including an untestable generic gate array circuit, each circuit including M-1 generically-patterned metal interconnection layers and an Mth unpatterned metal interconnection layer, wherein each generic gate array circuit is not yet electrically operative; and

a self-contained electrical testing circuit having probe pads on the Mth metal interconnection layer, wherein the self-contained electrical testing circuit is accessible through the probe pads and is electrically functional.

14. An integrated circuit wafer as in claim 13,

wherein the self-contained electrical testing circuit is operative to test metal resistance on each metal layer.

15. An integrated circuit wafer as in claim 13, wherein the self-contained electrical testing circuit is operative to test etch quality on each metal layer.

16. An integrated circuit wafer as in claim 13, wherein the self-contained electrical testing circuit is located in a scribe line area between the plurality of generic gate array dies.

17. An integrated circuit wafer as in claim 13, wherein the self-contained electrical testing circuit is located within an active area of the generic gate array dies.

18. An integrated circuit wafer as in claim 13, wherein M is four.