Silicon carbide semiconductor device and process for manufacturing same

• US 6,133,587 A
• Filed: 02/13/1998
• Issued: 10/17/2000
• Est. Priority Date: 01/23/1996
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Takeuchi, Yuichi, Fuma, Hiroo, Murata, Toshio, Tokura, Norihito, Miyajima, Takeshi, Suzuki, Takamasa, Onda, Shoichi
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/023,280
• Time in Patent Office: 977 Days
• Field of Search: 257/354, 257/77, 257/331
• US Class Current: 257/77
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A n^- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n⁺ -type source region 5, which trench 7 passes through the n⁺ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n^- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

Claims

1. A silicon carbide semiconductor device, comprising:

a single crystal silicon carbide semiconductor substrate comprising a stack of a first semiconductor layer of a first conductive-type, a second embodiment layer of the first conductive-layer having an electric resistance higher than that of said first semiconductor layer, and a third semiconductor layer of a second conductive-type different from the first conductive-type in this order from the bottom to the top thereof, and single crystal silicon carbide semiconductor substrate having a main surface on a side of said third semiconductor layer;

a first semiconductor region of the first conductive-type formed in a predetermined region of said third semiconductor layer;

a trench extending from said main surface through said first semiconductor region and said third semiconductor layer and reaching said second semiconductor layer, said trench having a side wall exposing said first semiconductor region and said third semiconductor layer and a bottom exposing said second semiconductor layer;

an island semiconductor region comprising said first semiconductor region and said third semiconductor layer and entirely surrounded by said trench so as to be separated from any other island semiconductor regions;

a gate insulating layer formed on the side wall of said island semiconductor region;

a gate electrode layer formed on said gate insulating layer;

a first electrode layer formed on at least a portion of said first semiconductor region; and

a second electrode layer formed on a surface of said first semiconductor layer.

2. The silicon carbide semiconductor device according to claim 1, wherein said island semiconductor region has a polygonal shape in a plan view from the tope of said stack and each of the interior angles of said polygonal shape is less than 180°

.

3. The silicon carbide semiconductor device according to claim 2, wherein each side of said polygonal shape is almost in parallel with [1100] and said gate insulating layer is a thermally oxidized layer formed by thermal oxidation in a wet atmosphere.

4. The silicon carbide semiconductor device according to claim 3, wherein said polygonal shape is a hexagonal shape having substantially equal interior angles.

5. The silicon carbide semiconductor device according to claim 1, wherein said main surface of said single crystal silicon carbide semiconductor substrate has a carbon face of (0001), said island semiconductor region has side walls extending in the [1120] directions, wherein the trench exposes side walls of the first semiconductor region and third semiconductor layer and at least one of a side wall and a top wall of the second semiconductor layer and said semiconductor device further comprises a fourth semiconductor layer of silicon carbide grown and extending on said side walls of said first semiconductor region and said third semiconductor layer and at least one of the side wall and the top wall of said second semiconductor layer, said fourth semiconductor layer having a surface on which said gate insulating layer is formed;

said fourth semiconductor layer separating the first semiconductor region and the third semiconductor layer from the gate insulating layer.

6. The silicon carbide semiconductor device according to claim 1, comprising a plurality of island semiconductor regions separated from each other.

7. The silicon carbide semiconductor device according to claim 5, wherein the fourth semiconductor layer is of the first conductive type.