High voltage complementary semiconductor device (HV-CMOS) with gradient doping electrodes

• US 6,133,606 A
• Filed: 05/12/1999
• Issued: 10/17/2000
• Est. Priority Date: 05/12/1999
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tung, Ming-Tsung
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/310,239
• Time in Patent Office: 524 Days
• Field of Search: 257/330, 257/332, 257/333, 257/334, 257/339, 257/389, 257/900, 438/272, 438/271, 438/270
• US Class Current: 257/332
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A structure of high voltage semiconductor devices having N-well 1 and N-well 2 formed with two different doping densities acting as a gradient doping of a drift region. This structure results in a lift in its current drive capability and as well as in its breakdown voltage. The structure further comprises a buried spacer oxide, serving as a point of exertion for the edges of the buried gate electrode. And finally, since the gate electrode is formed by a trenching method, not only is the channel length increased with the placement of both the channel and drift regions changes in the to vertical direction, all of those contribute to a great reduction in the occupied chip area.

Claims

1. A high voltage semiconductor device, comprising:

a semiconductor substrate;

a first trench formed inside said substrate to a first depth;

a second trench formed inside said substrate to a second depth;

a pair of source and drain regions formed on the left side and right side of said first trench and said second trench respectively, moreover, said pair of source and drain regions being formed within said substrate and having a depth approximately equal to said second depth of said second trench;

a first doping region formed within said pair of source and drain regions, wherein the conductivity type of a first dopant is opposite the conductivity type of said substrate;

a second doping region formed within said pair of source and drain regions and positioned directly above said first doping region, wherein the conductivity type of a second dopant is the same as the conductivity type of said first doping region, moreover, the doping density of said second doping region is higher than the doping density of said first doping region;

a third doping region formed within said pair of source and drain regions and positioned directly above said second doping region, wherein the top surface of said third doping region is the uppermost surface of said pair of source and drain regions, the conductivity type of a third dopant being the same as the conductivity type of said second doping region, moreover, the doping density of said third doping region being higher than the doping density of said second doping region;

a spacer formed on sidewalls of said first trench and also occupies a bottom portion of said first trench;

a gate oxide layer formed on sidewalls and on a bottom surface of said second trench;

a buried gate electrode formed on top of said gate oxide layer and also fills up said first trench and said second trench, wherein the top surface of said buried gate electrode has a height almost equal to the uppermost surface of said pair of source and drain regions.

2. The high voltage semiconductor device as recited in claim 1, wherein said first depth of said first trench is equal to the depth of said second doping region or is at a level slightly higher than the bottom of said first doping region.

3. The high voltage semiconductor device as recited in claim 1, wherein said second depth of said second trench is either slightly above or slightly below the bottom of said first doping region.

4. The high voltage semiconductor device as recited in claim 1, wherein said second trench is deeper inside said substrate than said first trench, and the width of said second trench is smaller than the width of said first trench.

5. The high voltage semiconductor device as recited in claim 1, wherein said first and second doping region constitute a grading doping for a drift region.

6. The high voltage semiconductor device as recited in claim 1, wherein the shape of said gate oxide layer is a "U"-type shape and represents a channel length between said source region and said drain region.

7. The high voltage semiconductor device as recited in claim 1, wherein said spacer is formed within said substrate and functions as a point of exertion and also as an isolation layer.

8. The high voltage semiconductor device as recited in claim 7, wherein said spacer is located between said source/drain region and said buried gate electrode.

9. The high voltage semiconductor device as recited in claim 7, wherein said spacer comprises silicon oxide or silicon nitride.

10. The high voltage semiconductor device as recited in claim 1, wherein said semiconductor substrate comprises silicon.

11. The high voltage semiconductor device as recited in claim 1, wherein said semiconductor substrate has p-type conductivity.

12. The high voltage semiconductor device as recited in claim 1, wherein said buried gate electrode comprises polysilicon, polysilicon compound, or metal.

13. The high voltage semiconductor device as recited in claim 1, wherein said first, second, and third doping regions of said pair of source and drain regions comprises n-type doped semiconductor.