Metal layer interconnects with improved performance characteristics

• US 6,133,628 A
• Filed: 12/18/1997
• Issued: 10/17/2000
• Est. Priority Date: 12/18/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US08/993,061
• Time in Patent Office: 1,034 Days
• Field of Search: 257/700, 257/691, 257/698, 257/758
• US Class Current: 257/698
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Two patterned metal layers are interconnected by forming a through-hole in one or more insulating layers, employing an etch process minimizing the formation of polymeric residue, thereby maintaining an appropriate etch rate to penetrate the insulating material. A variety of fluorocarbon gas chemistries may be used, such as CF₄, CH₃, CHF₃ and NF₃. The through-hole is then filled with a conductive material, such as tungsten, to form a conductive via.

Claims

1. A semiconductor device comprising:

a substrate;

a first dielectric layer formed on the substrate;

a first patterned metal layer on the first dielectric layer;

a second dielectric layer on the first patterned metal layer;

a second patterned metal layer on the second dielectric layer;

a third dielectric layer on the second patterned metal layer;

a third patterned metal layer on the third dielectric layer; and

a conductive via providing a direct electrical connection between the first and third patterned metal layers without a landing pad on the second patterned metal layer, wherein the conductive via comprises;

a through-hole formed in both the second and third dielectric layers exposing the first patterned metal layer without exposing any metal of the second patterned metal layer; and

a conductive plug filling the through-hole and forming a direct electrical connection between the first and third patterned metal layers; and

the combined thickness of the second and third dielectric layers at the through-hole is from about 2.8 to about 3.5 microns.

2. The semiconductor device according to claim 1, wherein the aspect ratio of the through-hole is about 5.0 to about 10.0.

3. A semiconductor device comprising:

first and second conductive layers spaced apart by one or more insulating layers;

a through-hole having an aspect ratio of about 5.0 to about 10.0 formed in the insulating layers exposing the first conductive layer, wherein the one or more insulating layers have a total thickness of about 2.8 to about 3.5 microns; and

a conductive material filling the through-hole and electrically interconnecting the first and second conductive layers.

4. The semiconductor device according to claim 3, wherein the one or more insulating layers have a total thickness of at least about 3.5 microns.