Three-dimensional structure memory

• US 6,133,640 A
• Filed: 11/17/1997
• Issued: 10/17/2000
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US08/971,565
• Time in Patent Office: 1,065 Days
• Field of Search: 257/778, 257/777
• US Class Current: 257/778
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 29/848 by adjacent switching
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/29109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/29118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. A stacked integrated circuit memory comprising:

a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit;

at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and

a bond bonding together the first substrate and the substantially flexible substrate, the bond having a withstand temperature compatible with comparatively high temperature semiconductor processes.

2. The apparatus of claim 1, wherein the first substrate has formed thereon the memory circuit and is part of a stack of memory circuit substrates, and the second substrate has formed thereon the memory controller circuit.

3. The apparatus of claim 2, wherein the first and second substrates are singulated die, the second substrate having greater area than the first substrate.

4. The apparatus of claim 3, wherein the second substrate has formed thereon additional circuitry separate from the memory controller circuit.

5. The apparatus of claim 4, wherein the additional circuitry is part of a graphics display subsystem.

6. The apparatus of claim 4, wherein the additional circuitry comprises a microprocessor.

7. The apparatus of claim 1, wherein the substantially flexible substrate includes memory I/O pads.

8. The apparatus of claim 7, wherein the memory circuit is formed proximate a top surface of the substantially flexible substrate, the top surface being bonded to the first substantially rigid substrate, and the memory I/O pads are formed proximate an opposite bottom surface of the substantially flexible substrate.

9. The apparatus of claim 1, wherein the memory circuit and the memory controller circuit are coupled by vertical interconnects.

10. The apparatus of claim 9, wherein said vertical interconnects include fine-grain vertical interconnects formed at a pitch of less than 100 μ

m.

11. The method of claim 10, wherein at least some of the fine-grain vertical interconnects are arrayed in two dimensions.

12. The apparatus of claim 10, wherein said memory circuit comprises a two-dimensional array of memory blocks, each memory block having formed proximate thereto an array of fine-grain vertical interconnects forming a first port coupling the memory block to the memory controller.

13. The apparatus of claim 12, wherein at least some memory blocks have formed proximate thereto an array of fine-grain vertical interconnects forming a second port coupling the memory block to the memory controller.

14. The apparatus of claim 1, wherein at least one of said memory circuits provides redundant memory locations.

15. The apparatus of claim 14, further comprising an additional substantially flexible substrate on which is formed a redundant memory circuit.

16. The apparatus of claim 15, wherein the memory controller circuit comprises ECC logic and is programmed to store ECC syndromes in the redundant memory circuit.

17. The apparatus of claim 14, wherein the memory controller circuit comprises logic for testing the memory circuit.

18. The apparatus of claim 17, wherein the memory controller circuit is programmed to substitute redundant memory locations for defective memory locations in the memory circuit.

19. The apparatus of claim 1, wherein the memory controller circuit comprises logic for performing at least one of the following functions:

virtual memory management, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management, and database processing.

20. The apparatus of claim 1, further comprising a substrate having formed thereon a redundant memory controller, bonded to the substantially flexible substrate.

21. The apparatus of claim 1, further comprising a substrate having formed thereon a microprocessor, bonded to the substantially flexible substrate.

22. The apparatus of claim 1, wherein the memory controller circuit comprises sense amplifiers coupled to data lines of the memory circuit.

23. The apparatus of claim 22, wherein the sense amplifiers discriminate between more than two signal levels, each sense amplifier producing a multi-level output signal.

24. The apparatus of claim 22, wherein the sense amplifiers are sized so as to exhibit a switching speed of about 10 ns or less.

25. The apparatus of claim 1, wherein said memory controller circuit is fabricated using a semiconductor process technology, characterized by a particular deposition sequence, and said memory circuits are formed using a different process technology characterized by a different deposition sequence.

26. The apparatus of claim 25, wherein said different process technology is selected from a group consisting of:

DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

27. The apparatus of claim 8 wherein said top surface and said first substantially rigid substrate include both interconnect metallization and non-interconnect metallization and are bonded together by thermal diffusion bonding, whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.

28. A stacked integrated circuit memory comprising:

a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit;

at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and

a compact two-dimensional array of fine-grain vertical interconnects interior to and extending between the first substrate and the substantially flexible substrate, interconnecting integrated circuitry formed on the first substrate and the substantially flexible substrate.

29. The apparatus of claim 28, wherein the first substrate has formed thereon the memory circuit and is part of a stack of memory circuit substrates, and the second substrate has formed thereon the memory controller circuit.

30. The apparatus of claim 28, wherein the substantially flexible substrate includes memory I/O pads.

31. The apparatus of claim 28, wherein the memory circuit and the memory controller circuit are coupled by vertical interconnects.

32. The apparatus of claim 28, wherein at least one of said memory circuits provides redundant memory locations.

33. The apparatus of claim 28, wherein the memory controller circuit comprises logic for performing at least one of the following functions:

virtual memory management, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management, and database processing.

34. The apparatus of claim 28, further comprising a second substrate having formed thereon a redundant memory controller, bonded to the substantially flexible substrate.

35. The apparatus of claim 28, further comprising a second substrate having formed thereon a microprocessor, bonded to the substantially flexible substrate.

36. The apparatus of claim 28, wherein the memory controller circuit comprises sense amplifiers coupled to data lines of the memory circuit.