Semiconductor integrated circuit having tri-state logic gate circuit

• US 6,133,752 A
• Filed: 04/07/1998
• Issued: 10/17/2000
• Est. Priority Date: 09/25/1997
• Status: Expired due to Fees

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kawagoe, Masakuni
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/055,988
• Time in Patent Office: 924 Days
• Field of Search: 326/56, 326/57, 326/58, 326/80, 326/81, 326/83, 326/86, 326/88, 326/101, 326/103, 97/99
• US Class Current: 326/55
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

The tri-state logic gate circuit is preferably made up of a first inverter circuit which selectively outputs one of the power supply voltage and a ground potential, a second inverter circuit which selectively outputs one of the first inverter circuit output and the boosted power supply voltage, a resistor connected between the first and second inverter circuits, and a latch circuit. Accordingly, the tri-state logic gate circuit can avoid latch-up.

Claims

1. A tri-state logic gate circuit comprising:

a first inverter circuit selectively outputting one of a power supply voltage and a ground potential;

a second inverter circuit selectively outputting one of an output of the first inverter circuit and a boosted power supply voltage;

a resistor connected between the first and second inverter circuits;

a negative voltage generating circuit; and

an input/output circuit arranged near the negative voltage generating circuit.

2. A tri-state logic gate circuit as claimed in claim 1, wherein the first inverter circuit comprises CMOS circuitry.

3. A tri-state logic gate circuit as claimed in claim 2, wherein the CMOS circuitry including a P-channel MOS transistor which is supplied an power supply voltage to a back-bias thereof.

4. A tri-state logic gate circuit as claimed in claim 3, wherein the power supply voltage is an external power supply voltage.

5. A tri-state logic gate circuit as claimed in claim 4, wherein the back-bias supply source providing plural supply source per supply line.

6. A tri-state logic gate circuit as claimed in claim 1, wherein the input/output circuit is surrounded by a guard ring.

7. A tri-state logic gate circuit comprising:

a first inverter circuit being a bootstrap circuitry, the first inverter circuit selectively outputting one of a power supply voltage and a ground potential;

a second inverter circuit selectively outputting one of an output of the first inverter circuit and a boosted power supply voltage;

a negative voltage generating circuit; and

an input/output circuit arranged near the negative voltage generating circuit.

8. A tri-state logic gate circuit as claimed in claim 7, wherein the first inverter circuit comprises a pair of N-channel transistors.

9. A tri-state logic gate circuit as claimed in claim 8, further comprising:

a level shift circuit which drives one of the pair of N-channel transistors; and

a third inverter which complimentary operates the pair of N-channel transistors.

17. A tri-state logic gate circuit as claimed in claim 7, wherein the input/output circuit is surrounded by a guard ring.

10. A tri-state logic gate circuit comprising:

a latch circuit;

a first inverter circuit selectively outputting one of a power supply voltage and a ground potential;

a second inverter circuit selectively outputting one of an output of the first inverter circuit and a boosted power supply voltage and inputting an output of the latch circuit;

a resistor connected between the first and second inverter circuits;

a negative voltage generating circuit; and

an input/output circuit arranged near the negative voltage generating circuit.

11. A tri-state logic gate circuit as claimed in claim 10, wherein the first inverter circuit comprises CMOS circuitry.

12. A tri-state logic gate circuit as claimed in claim 11, wherein the CMOS circuitry including a P-channel MOS transistor which is supplied a power supply voltage to a back-bias thereof.

13. A tri-state logic gate circuit as claimed in claim 12, wherein the power supply voltage is an external power supply voltage.

14. A tri-state logic gate circuit as claimed in claim 13, wherein the back-bias supply source providing plural supply source per supply line.

15. A tri-state logic gate circuit as claimed in claim 10, wherein the input/output circuit is surrounded by a guard ring.

16. A pair of tri-state logic gate circuit comprising:

a first tri-state logic gate circuit including a first inverter circuit selectively outputting one of a power supply voltage and a ground potential, a second inverter circuit selectively outputting one of an output of the first inverter circuit and a boosted power supply voltage, a negative voltage generating circuit, and an input/output circuit arranged near the negative voltage generating circuit;

a second tri-state logic gate circuit including a third inverter circuit selectively outputting one of a power supply voltage and a ground potential, a fourth inverter circuit selectively outputting one of an output of the first inverter circuit and a boosted power supply voltage, a negative voltage generating circuit, and an input/output circuit arranged near the negative voltage generating circuit;

the first inverter circuit operating using a driving signal of the fourth inverter circuit; and

the third inverter circuit operating using a driving signal of the second inverter circuit.

18. A pair of tri-state logic gate circuits as claimed in claim 16, wherein each input/output circuit is surrounded by a guard ring.