Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)
First Claim
1. A one-place signal processing circuit for multiple-valued logic, comprising:
- an input and an output,a first terminus branch coupling said input to said output, said first terminus branch conducting a first output signal for a first set of unique input signals;
a second terminus branch coupling said input to said output, said second terminus branch conducting a second output signal for a second set of unique input signals; and
an intermediate branch coupling said input to said output, said intermediate branch having only two switches and conducting a third output signal for a third set of unique input signals;
wherebya one-place logic function is provided for multiple-valued logic signal processing.
5 Assignments
0 Petitions
Accused Products
Abstract
Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than 1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.
-
Citations
26 Claims
-
1. A one-place signal processing circuit for multiple-valued logic, comprising:
-
an input and an output, a first terminus branch coupling said input to said output, said first terminus branch conducting a first output signal for a first set of unique input signals; a second terminus branch coupling said input to said output, said second terminus branch conducting a second output signal for a second set of unique input signals; and an intermediate branch coupling said input to said output, said intermediate branch having only two switches and conducting a third output signal for a third set of unique input signals;
wherebya one-place logic function is provided for multiple-valued logic signal processing. - View Dependent Claims (2)
-
-
3. A multiple-place signal processing circuit for multiple-valued logic, comprising:
-
first and second inputs; an output; a first composite branch coupling said first and second inputs to said output, said first composite branch having an intermediate branch, said intermediate branch having only two switches, said first composite branch conducting a first output signal for a first set of unique input signals; and a second composite branch coupling said first and second inputs to said output, said second composite branch conducting a second output signal for a second set of unique input signals;
wherebya multiple-place logic function is provided for multiple-valued logic signal processing. - View Dependent Claims (4)
-
-
5. An information signal processing circuit for multiple-valued logic, comprising:
-
a first switch, said first switch coupled to a first source voltage and having a first switch input and a first switch output, said first switch transmitting said first source voltage to said first switch output when an input signal voltage impressed upon said first switch input is sufficiently different than said first source voltage by a first threshold voltage; and a second switch, said second switch coupled to said first switch, said second switch coupled to a second source voltage and having a second switch input coupled to said first switch input and a second switch output coupled to said first switch output, said second switch transmitting said second source voltage to said second switch output when said input signal voltage impressed upon said second switch input is sufficiently different than said second source voltage by a second threshold voltage;
wherebythe information signal processing circuit controls transmission of either said first source voltage or said second source voltage in response to said input signal voltage by appropriate selection of said first switch, said first threshold voltage required by said first switch, said second switch, and said second threshold voltage required by said second switch thereby attaining a multiple-valued logic circuit. - View Dependent Claims (6, 7, 8)
-
-
9. An information signal processing circuit for multiple-valued logic, comprising:
-
a first N-channel FET switch, said first switch coupled to a first source voltage and having a first switch input and a first switch output, said first switch transmitting said first source voltage to said first switch output when an input signal voltage impressed upon said first switch input is sufficiently different than said first source voltage by a first threshold voltage; a second P-channel FET switch, said second switch coupled to a second source voltage and having a second switch input coupled to said first switch input and a second switch output coupled to said first switch output, said second switch transmitting said second source voltage to said second switch output when said input signal voltage impressed upon said second switch input is sufficiently different than said second source voltage by a second threshold voltage; and said first source voltage plus said first threshold voltage overlapping said second source voltage plus said second threshold voltage to provide continuous output;
wherebythe information signal processing circuit controls transmission of either said first source voltage or said second source voltage in response to said input signal voltage by appropriate selection of said first switch, said first threshold voltage required by said first switch, said second switch, and said second threshold voltage required by said second switch thereby attaining a multiple-valued logic circuit.
-
-
10. A multiple-valued logic signal processing circuit for processing signals having three or more levels, comprising:
-
a first input; an output; a first terminus branch coupled to said first input and to said output, said first terminus branch responding to input signals of a first logic level carried by said first input by transmitting a first output signal; a second terminus branch coupled to said first input and to said output, said second terminus branch responding to input signals of a second logic level carried by said first input by transmitting a second output signal; a first intermediate branch coupled to said first input and said outputs said first intermediate branch having only two switches and responding to input signals of a third logic level carried by said first input by transmitting a third output signal; said first terminus branch not transmitting said first output signal when said first input carries said second logic level signal; and said second terminus branch not transmitting said second output signal when said first input carries said first logic level signal;
wherebylogic operations are performed on input signals by the signal processing circuit, said input signals controlling said output signals. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
-
25. A multiple-valued logic signal processing circuit for processing signals having three or more levels, comprising:
-
a first input; a second input; an output; a first terminus branch coupled to said first input and to said output, said first terminus branch responding to input signals of a first logic level carried by said first input by transmitting a first output signal; a second terminus branch coupled to said first input and to said output, said second terminus branch responding to input signals of a second logic level carried by said first input by transmitting a second output signal; a third terminus branch coupled to said second input and said output, said third terminus branch responding to input signals of a third logic level carried by said second input by transmitting a third output signal; a fourth terminus branch coupled to said second input and said output, said fourth terminus branch responding to input signals of a fourth logic level carried by said second input by transmitting a fourth output signal; said first and third terminus branches forming a first composite branch capable of transmitting a first composite output signal; said second and fourth terminus branches forming a second composite branch capable of transmitting a second composite output signal; said first composite branch only transmitting said first composite output signal when said first and third logic level signals are carried by said first and second inputs, respectively; said second composite branch only transmitting said second composite output signal when said second and fourth logic level signals are carried by said first and second inputs, respectively;
wherebya multiple-place multiple-valued logic circuit is provided that provides unique output logic signals in response to unique first and second input logic signals. - View Dependent Claims (26)
-
Specification