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Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC)

  • US 6,133,754 A
  • Filed: 05/29/1998
  • Issued: 10/17/2000
  • Est. Priority Date: 05/29/1998
  • Status: Expired due to Term
First Claim
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1. A one-place signal processing circuit for multiple-valued logic, comprising:

  • an input and an output,a first terminus branch coupling said input to said output, said first terminus branch conducting a first output signal for a first set of unique input signals;

    a second terminus branch coupling said input to said output, said second terminus branch conducting a second output signal for a second set of unique input signals; and

    an intermediate branch coupling said input to said output, said intermediate branch having only two switches and conducting a third output signal for a third set of unique input signals;

    wherebya one-place logic function is provided for multiple-valued logic signal processing.

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