Conductive epoxy flip-chip package and method

• US 6,134,118 A
• Filed: 04/03/1997
• Issued: 10/17/2000
• Est. Priority Date: 01/19/1995
• Status: Expired due to Term

• Current Assignee: Vertical Circuits Solutions, Inc.
• Original Assignee: Cubic Memory, Inc.
• Inventors: Pedersen, David V., Finley, Michael G., Sautter, Kenneth M.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US08/834,798
• Time in Patent Office: 1,293 Days
• Field of Search: 28/841-844, 28/623.4, 28/855, 174/260, 174/261, 174/117 A, 174/259, 257/737, 257/738, 257/700, 257/723, 257/724, 257/746, 257/760, 257/767, 257/768-770, 257/773, 257/774, 257/779, 257/772, 257/778, 257/782, 257/780, 257/783, 257/692 , 257/698, 438/612, 438/613, 438/108, 361/760, 361/772, 361/773, 361/777, 361/779, 361/783, 439/68, 439/83, 156/276, 252/512, 252/514
• US Class Current: 361/779
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29399 Coating material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/753 by means of pressure
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/5256 : comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5328 : containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01R 29/00 : Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors
• CPC Class Codes: H01R 4/04 : using electrically conductive adhesives
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10719 : Land grid array [LGA]
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: H05K 3/321 : by conductive adhesives
• CPC Class Codes: H05K 7/023 : Stackable modules
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49171 : with encapsulating

Abstract

A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. The inner bonds are rerouted by covering the chip with a first insulation layer and opening the first insulation layer over the inner bond pads. A metal layer is then disposed over the first insulation layer in contact with the inner bond pads. A second insulation layer is disposed over the metal layer, and the second insulation layer is opened to expose selected portions of the metal layer to form external connection points. Electrically conductive epoxy is then disposed between the external connection points of the semiconductor chip and the terminals of the substrate, thereby electrically connecting the semiconductor chip to the substrate.

Claims

1. A semiconductor chip package, comprising:

a substrate having a plurality of terminals;

a semiconductor chip on said substrate, said semiconductor chip including;

a plurality of bond pads,

a first insulation layer covering said chip,

a first plurality of holes in said first insulation layer exposing said bond pads,

a metal layer deposited over said first insulation layer to form an electrical contact with said bond pads,

a second insulation layer deposited over said metal layer, and

a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points such that said metal layer routes respective bond pads to corresponding external connection points; and

electrically conductive epoxy applied between said external connection points of said semiconductor chip and said terminals of said substrate, thereby electrically connecting said semiconductor chip to said substrate.

2. A semiconductor chip package as in claim 1, wherein said substrate is a printed circuit board.

3. A semiconductor chip package as in claim 2, wherein said semiconductor chip includes four edges and said external contact points are located on said semiconductor chip internally from said edges.

4. A semiconductor chip package as in claim 1, wherein said semiconductor chip is placed on said substrate face-down such that said external connection points are positioned directly above said terminals on said substrate.

5. A semiconductor chip package as in claim 1, wherein said semiconductor chip is placed on said substrate face-up such that said external connection points face-away from said terminals on said substrate.

6. A semiconductor chip package as in claim 5, wherein said semiconductor chip includes four edges and said external contact points are located along the edges of said semiconductor chip.

7. A semiconductor chip package as in claim 6, wherein said semiconductor chip includes beveled edge walls and said electrically conductive epoxy extends down from said external contact points along said beveled edge walls to said terminals on said substrate.

8. The package as in claim 1 including means for maintaining a minimum bond thickness between said chip and said substrate.

9. The package as in claim 8 wherein said means for maintaining include at least one sphere of known thickness which lies between said external connection points and said terminals.

10. The package as in claim 9 wherein said at least one sphere is a glass sphere.

11. A method for producing a multichip package, said method comprising the steps of:

providing bond pads on said chip;

covering said chip with a first insulation layer;

forming a first plurality of holes in said first insulation layer to expose said bond pads;

depositing a metal layer over said first insulation layer such that said metal layer is in electrical contact with said bond pads;

depositing a second insulation layer over said metal layer;

exposing selected portions of said metal layer to form external connection points such that said metal layer routes respective bond pads to corresponding external connection points;

providing a substrate having a plurality of terminals; and

applying conductive epoxy between said external connection points of said chip and said terminals of said substrate to electrically connect said chip to said substrate.

12. A method as in claim 11, further comprising the step of placing said chip on said substrate face-down such that said external connection points are positioned directly above said terminals on said substrate.

13. A method as in claim 12, further comprising the steps of:

providing said chip with four edges; and

forming said external contact points on said chip internally from said edges.

14. A method as in claim 11, further comprising the step of placing said chip face-up on said substrate such that said external connection points face-away from said terminals on said substrate.

15. A method as in claim 14, further comprising the steps of:

providing said chip with four edges; and

forming said external contact points along the edges of said chip.

16. A method as in claim 15, further comprising the steps of:

providing said chip with beveled edge walls; and

dispensing said electrically conductive epoxy from said external contact points along said beveled edge walls to said terminals on said substrate.

17. A flip-chip package, comprising:

a printed circuit board having a plurality of terminals;

a flip-chip including,

four edges;

a plurality of bond pads,

a first insulation layer covering said flip-chip,

a first plurality of holes in said first insulation layer exposing said bond pads,

a metal layer deposited over said first insulation layer in electrical contact with said bond pads

a second insulation layer deposited over said metal layer, and

a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points such that said metal layer routes respective bond pads to corresponding external connection points, said external connection points being located on said flip-chip internally from said edges;

said flip-chip placed on said printed circuit board face-down such that said external connection points are positioned directly above said terminals on said printed circuit board; and

electrically conductive epoxy applied between said external connection points of said flip-chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board.

18. A chip package, comprising:

a printed circuit board having a plurality of terminals;

a chip including,

four edges;

a plurality of bond pads,

a first insulation layer covering said chip,

a first plurality of holes in said first insulation layer exposing said bond pads,

a metal layer deposited over said first insulation layer in electrical contact with said bond pads

a second insulation layer deposited over said metal layer,

a second plurality of holes in said second insulation layer exposing selected portions of said metal layer to form external connection points such that said metal layer routes respective bond pads to corresponding external connection points, said external connection points being located along said edges of said chip, and

beveled edge walls located at the outer edges of said chip and sloping toward the center of said chip;

said chip placed on said printed circuit board face-up; and

electrically conductive epoxy applied along said beveled edge walls between said external contact points of said chip and said terminals of said printed circuit board, thereby electrically connecting said chip to said printed circuit board.