Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories
First Claim
1. A method for programming a memory cell, comprising:
- connecting a bias circuit to charge a line that is coupled to a control gate of the memory cell;
disconnecting the bias circuit from the line, wherein charge remains trapped on the line and controls a first programming voltage on the control gate of the memory cell; and
applying a second programming voltage to a drain of the memory cell, wherein a combination of the first programming voltage on the control gate, the second programming voltage on the drain, and a voltage on a source of the memory cell changes a threshold voltage in the memory cell.
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Accused Products
Abstract
A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.
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Citations
17 Claims
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1. A method for programming a memory cell, comprising:
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connecting a bias circuit to charge a line that is coupled to a control gate of the memory cell; disconnecting the bias circuit from the line, wherein charge remains trapped on the line and controls a first programming voltage on the control gate of the memory cell; and applying a second programming voltage to a drain of the memory cell, wherein a combination of the first programming voltage on the control gate, the second programming voltage on the drain, and a voltage on a source of the memory cell changes a threshold voltage in the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for programming a memory cell, comprising:
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connecting a bias circuit to charge a line that is coupled to a control gate of the memory cell, wherein the memory cell is in a first array from among a plurality of memory arrays in a non-volatile memory, and the line is a first row coupled to control gates of a row of memory cells in the first array; disconnecting the bias circuit from the line, wherein charge remains trapped on the line and controls a first programming voltage on the control gate of the memory cell; and applying a second programming voltage to a drain of the memory cell, wherein a combination of the first programming voltage on the control gate, the second programming voltage on the drain, and a voltage on a source of the memory cell changes a threshold voltage in the memory cell; connecting the bias circuit to charge a second row line in a second array from among the plurality of memory arrays, the second row line being coupled to a control gate of a second memory cell in the second array; using the bias circuit to charge the second row line for programming operation to be performed on the second memory cell; and performing the programming operation on the second memory cell while also programming the memory cell in the first array. - View Dependent Claims (13, 14, 15)
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16. A non-volatile memory comprising:
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a plurality of memory arrays, each memory array including memory cells arranged in rows and columns, row lines with each row line being coupled control gates of memory cells that are in a row of memory cells associated with the row line, and a row decoder coupled to the row lines; a bias circuit having a input port for a date signal, the bias circuit generating a bias signal having a voltage that depends on a value of the date signal; and a control circuit coupled to the bias circuit and the plurality of memory arrays, the control circuit selecting which of the plurality of arrays receives the bias signal from the bias circuit, wherein; during a first charging period of a write operation, the control circuit connects the bias circuit to the row decoder in a first array from among the plurality of arrays, and the bias circuit charges a selected row line in the first array for programming a first memory cell which is in the first array; during a second charging period of the write operation, the control circuit connects the bias circuit to the row decoder in a second array from among the plurality of arrays, and the bias circuit charges a selected row line in the second array for programming a second memory cell which is in the second array; and the second charging period occurs during programming of the first memory cell. - View Dependent Claims (17)
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Specification