Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories

• US 6,134,141 A
• Filed: 12/31/1998
• Issued: 10/17/2000
• Est. Priority Date: 12/31/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Wong, Sau-Ching
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US09/224,656
• Time in Patent Office: 656 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.23, 365/185.22, 365/185.25, 365/185.01
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5645 Multilevel memory with current-mirror arrangements
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A write process and circuit for a non-volatile memory such as a multi-bit-per-cell Flash memory has multiple local memory arrays and a global bias circuit that charges row lines in the arrays for programming operations. A programming operation in an array includes a charging period during which the global bias circuit charges a selected row line to a voltage corresponding to a value to be written in a memory cell and a sequence of program cycles and verify cycles during which the selected row line is isolated to preserve the charge from the bias circuit. A global control circuit can use a capacitive coupling to the charged row line to raise and lower the row line voltage. In one embodiment, the row line voltage rises to a programming voltage to change the threshold voltage of the selected cell during program cycles and falls to a verify voltage during verify cycles to sense whether the selected cell has a target threshold voltage. Alternatively, the row line voltage remains constant as charged by the bias circuit if a maximum current for biasing a column line connected to a sense amplifier causes the programming voltage to be equal to the trip point of the sense amplifier when the memory cell has the target threshold voltage.

Claims

1. A method for programming a memory cell, comprising:

connecting a bias circuit to charge a line that is coupled to a control gate of the memory cell;

disconnecting the bias circuit from the line, wherein charge remains trapped on the line and controls a first programming voltage on the control gate of the memory cell; and

applying a second programming voltage to a drain of the memory cell, wherein a combination of the first programming voltage on the control gate, the second programming voltage on the drain, and a voltage on a source of the memory cell changes a threshold voltage in the memory cell.

2. The method of claim 1, wherein the bias circuit charges the line to a first voltage, and the method further comprises capacitively coupling a second voltage to the line to raise the line from the first voltage to the first programming voltage.

3. The method of claim 2, wherein the first voltage is a voltage at which a sense amplifier coupled to the line sense a change in conductivity of the memory cell when the memory cell has a target threshold voltage, the method further comprising:

(a) capacitively coupling the second voltage to raise the line from the first voltage to the first programming voltage for a program cycle during which the threshold voltage in the memory cell changes;

(b) removing the second voltage from the capacitive coupling so that the line falls from the first programming voltage to the first voltage during a verify cycle;

(c) sensing the conductivity of the memory cell during the verify cycle; and

(d) repeating steps (a), (b) and (c) until sensing determines that the threshold voltage of the memory cell has reached the target threshold voltage.

4. The method of claim 3, further comprising selecting a maximum bias current for a column line coupled to a sense amplifier that performs the sensing, wherein the maximum bias current selected is such that second voltage, which is required to raise the line from the first voltage to the first programming voltage, is a supply voltage of an integrated circuit containing the memory cell.

5. The method of claim 1, wherein connecting the bias circuit to the line charges the line to the first programming voltage.

6. The method of claim 5, further comprising:

(a) applying the second programming voltage to the drain during a program cycle during which the threshold voltage in the memory cell changes;

(b) applying a second voltage to the drain during a verify cycle, wherein the control gate remains at a constant voltage through the program cycle and the verify cycle;

(c) sensing the conductivity of the memory cell during the verify cycle; and

(d) repeating steps (a), (b) and (c) until sensing determines that the threshold voltage of the memory cell has reached a target threshold voltage.

7. The method of claim 6, further comprising selecting a maximum bias current for a column line coupled to a sense amplifier that performs the sensing, wherein the maximum bias current selected is such that the first programming voltage corresponds to a trip point of the sense amplifier.

8. The method of claim 1, wherein the combination of the first programming voltage on the control gate, the second programming voltage on the drain, and the voltage on the source of the memory cell causes channel hot electron injection into a floating gate in the memory cell.

9. The method of claim 1, wherein the memory cell is in a first array from among a plurality of memory arrays in a non-volatile memory, and the line is a first row line coupled to control gates of a row of memory cells in the first array.

10. The method of claim 1, wherein connecting the bias circuit comprises:

applying a data signal to the bias circuit, the data signal indicating a value to be written in the memory cell;

generating from the bias circuit a first voltage that is selected according the value to be written; and

charging the line to the first voltage.

11. The method of claim 10, wherein the value is a multibit digital value.

12. A method for programming a memory cell, comprising:

connecting a bias circuit to charge a line that is coupled to a control gate of the memory cell, wherein the memory cell is in a first array from among a plurality of memory arrays in a non-volatile memory, and the line is a first row coupled to control gates of a row of memory cells in the first array;

disconnecting the bias circuit from the line, wherein charge remains trapped on the line and controls a first programming voltage on the control gate of the memory cell; and

applying a second programming voltage to a drain of the memory cell, wherein a combination of the first programming voltage on the control gate, the second programming voltage on the drain, and a voltage on a source of the memory cell changes a threshold voltage in the memory cell;

connecting the bias circuit to charge a second row line in a second array from among the plurality of memory arrays, the second row line being coupled to a control gate of a second memory cell in the second array;

using the bias circuit to charge the second row line for programming operation to be performed on the second memory cell; and

performing the programming operation on the second memory cell while also programming the memory cell in the first array.

13. The method of claim 12, wherein the programming operation on the second memory cell comprises:

disconnecting the bias circuit from the second row line, wherein charge remains trapped on the second row line and controls a third programming voltage on the control gate of the second memory cell; and

applying the second programming voltage to a drain of the second memory cell, wherein a combination of the third programming voltage on the control gate of the second memory cell, the second programming voltage on the drain of the second memory cell, and a voltage on a source of the second memory cell changes a threshold voltage in the second memory cell.

14. The method of claim 13, further comprising:

applying a data signal to the bias circuit

generating from the bias circuit a first voltage that is selected according a first value of the date signal, the first value being a data value to be written to the memory cell in the first array, wherein the bias circuit applies the first voltage to the first row line, the first voltage controlling the charge trapped on the first row line and thereby controlling the first programming voltage; and

generating from the bias circuit a second voltage that is selected according a second value of the date signal, the second value being a date value to be written to the second memory cell, wherein the bias circuit applies the second voltage to the second row line, the second voltage controlling the charge trapped on the second row line and thereby controlling the third programming voltage.

15. The method of claim 14, wherein the first value and the second value are multibit digital values.

16. A non-volatile memory comprising:

a plurality of memory arrays, each memory array including memory cells arranged in rows and columns, row lines with each row line being coupled control gates of memory cells that are in a row of memory cells associated with the row line, and a row decoder coupled to the row lines;

a bias circuit having a input port for a date signal, the bias circuit generating a bias signal having a voltage that depends on a value of the date signal; and

a control circuit coupled to the bias circuit and the plurality of memory arrays, the control circuit selecting which of the plurality of arrays receives the bias signal from the bias circuit, wherein;

during a first charging period of a write operation, the control circuit connects the bias circuit to the row decoder in a first array from among the plurality of arrays, and the bias circuit charges a selected row line in the first array for programming a first memory cell which is in the first array;

during a second charging period of the write operation, the control circuit connects the bias circuit to the row decoder in a second array from among the plurality of arrays, and the bias circuit charges a selected row line in the second array for programming a second memory cell which is in the second array; and

the second charging period occurs during programming of the first memory cell.

17. The memory of claim 16, wherein the memory is a multi-bit-per-cell memory.