Multi-state flash memory defect management

• US 6,134,143 A
• Filed: 11/19/1999
• Issued: 10/17/2000
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Norman, Robert D.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/443,661
• Time in Patent Office: 333 Days
• Field of Search: 365/185.03, 365/189.07, 365/200, 365/185.09, 365/185.11, 365/185.33, 395/182.04, 395/182.05
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A system is described which stores data intended for defective memory cells in a row of a memory array in an overhead location of the memory row. The data is stored in the overhead packet during a write operation, and is read from the overhead packet during a read operation. A defect location table for the row of the memory array is provided to identify when a defective memory cell is addressed for either a read or write access operation. During a write operation, the correct data is stripped from incoming data for storing into the overhead packet. During a read operation, the correct data is inserted into an output data stream from the overhead packet. Data written to defective cells can be either a custom setting, a default setting, or the original data. Shift registers are described for holding good data during either a read or write operation. The number of shift registers used is determined by the number of states stored in a memory cell. The shift registers use a marker for alignment of data bits in a data stream.

Claims

1. A memory device comprising:

an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory device;

a storage medium to store addresses of defective memory cells in the array; and

a data path circuit to receive incoming data bits to be written to the memory cells of the array, to store the incoming data bits to be written to the defective memory cells in the array as selected data bits, to output the selected data bits to be written to the overhead memory cells, and to output the incoming data bits to be written to the data memory cells.

2. The memory device of claim 1 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the array;

a defect management logic circuit comprising;

a defect table register being the storage medium to store addresses of defective memory cells in the array and to store replacement data bits to be written to the defective memory cells;

a working address pointer to receive and store an address of a memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the array;

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the array; and

wherein the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

3. A memory device comprising:

an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory device;

a storage medium to store addresses of defective multi-state memory cells in the array; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the array, to store the incoming data bits to be written to the defective multi-state memory cells in the array as selected data bits, to output the selected data bits to be written to the multi-state overhead memory cells, and to output the incoming data bits to be written to the multi-state data memory cells.

4. The memory device of claim 3 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the array;

a defect management logic circuit comprising;

a defect table register being the storage medium to store addresses of defective multi-state memory cells in the array and to store replacement data bits to be written to the defective multi-state memory cells;

a working address pointer to receive and store an address of a multi-state memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the array;

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells of the array; and

wherein the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

5. A system comprising:

one or more memory devices, each memory device comprising an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory devices;

a storage medium to store addresses of defective memory cells in the arrays; and

a data path circuit to receive incoming data bits to be written to the memory cells of the arrays, to store the incoming data bits to be written to the defective memory cells in the arrays as selected data bits, to output the selected data bits to be written to the overhead memory cells, and to output the incoming data bits to be written to the data memory cells.

6. The system of claim 5 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the arrays;

a defect management logic circuit comprising;

a defect table register to be the storage medium to store addresses of defective memory cells in the arrays and to store replacement data bits to be written to the defective memory cells;

a working address pointer to receive and store an address of a memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the arrays;

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the arrays; and

wherein the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

7. A system comprising:

one or more memory devices, each memory device comprising an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory devices;

a storage medium to store addresses of defective multi-state memory cells in the arrays; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the arrays, to store the incoming data bits to be written to the defective multi-state memory cells in the arrays as selected data bits, to output the selected data bits to be written to the multi-state overhead memory cells, and to output the incoming data bits to be written to the multi-state data memory cells.

8. The system of claim 7 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the arrays;

a defect management logic circuit comprising;

a defect table register to be the storage medium to store addresses of defective multi-state memory cells in the arrays and to store replacement data bits to be written to the defective multi-state memory cells;

a working address pointer to receive and store an address of a multi-state memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the arrays;

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells of the arrays; and

wherein the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

9. A memory device comprising:

an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory device; and

a data path circuit to receive incoming data bits to be written to the memory cells of the array, the data path circuit comprising;

a first storage medium to store addresses of defective memory cells in the array;

a logic circuit to compare an address in the array to receive one or more of the incoming data bits with the addresses of the defective memory cells;

a second storage medium to store the incoming data bits to be written to the defective memory cells in the array as selected data bits and to output the selected data bits to be written to the overhead memory cells; and

an output circuit to output the incoming data bits to be written to the memory cells of the array.

10. The memory device of claim 9 wherein:

the first storage medium comprises a defect table register to store addresses of defective memory cells in the array and to store replacement data bits to be written to the defective memory cells;

the logic circuit comprises;

a working address pointer to receive and store an address of a memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register; and

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

the second storage medium comprises a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells;

the output circuit comprises a multiplex circuit to output the incoming data bits to be written to the memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the array;

the data path circuit further comprises;

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the array; and

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the array; and

the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

11. A memory device comprising:

an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory device; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the array, the data path circuit comprising;

a first storage medium to store addresses of defective multi-state memory cells in the array;

a logic circuit to compare an address in the array to receive one or more of the incoming data bits with the addresses of the defective multi-state memory cells;

a second storage medium to store the incoming data bits to be written to the defective multi-state memory cells in the array as selected data bits and to output the selected data bits to be written to the multi-state overhead memory cells; and

an output circuit to output the incoming data bits to be written to the multi-state memory cells of the array.

12. The memory device of claim 11 wherein:

the first storage medium comprises a defect table register to store addresses of defective multi-state memory cells in the array and to store replacement data bits to be written to the defective multi-state memory cells;

the logic circuit comprises;

a working address pointer to receive and store an address of a multi-state memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register; and

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

the second storage medium comprises a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells;

the output circuit comprises a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the array;

the data path circuit further comprises;

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the array; and

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells of the array; and

the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

13. A system comprising:

one or more memory devices, each memory device comprising an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory devices;

a data path circuit to receive incoming data bits to be written to the memory cells of the arrays, the data path circuit comprising;

a first storage medium to store addresses of defective memory cells in the arrays;

a logic circuit to compare an address in the arrays to receive one or more of the incoming data bits with the addresses of the defective memory cells;

a second storage medium to store the incoming data bits to be written to the defective memory cells in the arrays as selected data bits and to output the selected data bits to be written to the overhead memory cells; and

an output circuit to output the incoming data bits to be written to the memory cells of the arrays.

14. The system of claim 13 wherein:

the first storage medium comprises a defect table register to store addresses of defective memory cells in the arrays and to store replacement data bits to be written to the defective memory cells;

the logic circuit comprises;

a working address pointer to receive and store an address of a memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register; and

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

the second storage medium comprises a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells;

the output circuit comprises a multiplex circuit to output the incoming data bits to be written to the memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the arrays;

the data path circuit further comprises;

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the arrays; and

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the arrays; and

the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

15. A system comprising:

one or more memory devices, each memory device comprising an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory devices; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the arrays, the data path circuit comprising;

a first storage medium to store addresses of defective multi-state memory cells in the arrays;

a logic circuit to compare an address in the arrays to receive one or more of the incoming data bits with the addresses of the defective multi-state memory cells;

a second storage medium to store the incoming data bits to be written to the defective multi-state memory cells in the arrays as selected data bits and to output the selected data bits to be written to the multi-state overhead memory cells; and

an output circuit to output the incoming data bits to be written to the multi-state memory cells of the arrays.

16. The system of claim 15 wherein:

the first storage medium comprises a defect table register to store addresses of defective multi-state memory cells in the arrays and to store replacement data bits to be written to the defective multi-state memory cells;

the logic circuit comprises;

a working address pointer to receive and store an address of a multi-state memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register; and

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

the second storage medium comprises a shift register to store the selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells;

the output circuit comprises a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the arrays;

the data path circuit further comprises;

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the arrays; and

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells in the arrays; and

the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

17. A memory device comprising:

an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory device; and

a data path circuit to receive incoming data bits to be written to the memory cells of the array, the data path circuit comprising;

a defect table register to store addresses of defective memory cells in the array and to store replacement data bits to be written to the defective memory cells;

a working address pointer to receive and store an address of a memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the incoming data bits to be written to the defective memory cells as selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the array.

18. The memory device of claim 17 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the array;

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the array; and

wherein the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

19. A memory device comprising:

an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory device; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the array, the data path circuit comprising;

a defect table register to store addresses of defective multi-state memory cells in the array and to store replacement data bits to be written to the defective multi-state memory cells;

a working address pointer to receive and store an address of a multi-state memory cell in the array selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the incoming data bits to be written to the defective multi-state memory cells as selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the array and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the array.

20. The memory device of claim 19 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the array;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the array;

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells of the array; and

wherein the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

21. A system comprising:

one or more memory devices, each memory device comprising an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory devices; and

a storage medium to store addresses of defective memory cells in the arrays; and

a data path circuit to receive incoming data bits to be written to the memory cells of the arrays, the data path circuit comprising;

a defect table register to store addresses of defective memory cells in the arrays and to store replacement data bits to be written to the defective memory cells;

a working address pointer to receive and store an address of a memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the incoming data bits to be written to the defective memory cells as selected data bits in response to the generation of the flag and to output the selected data bits to be written to the overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective memory cells in the arrays.

22. The system of claim 21 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the memory cells of the arrays;

a modifier logic circuit to modify the incoming data bits to be written to the memory cells of the arrays; and

wherein the memory cells comprise multi-state data memory cells and multi-state overhead memory cells.

23. A system comprising:

one or more memory devices, each memory device comprising an array of multi-state memory cells comprising multi-state data memory cells and multi-state overhead memory cells;

a controller to control read and write operations for the memory devices; and

a data path circuit to receive incoming data bits to be written to the multi-state memory cells of the arrays, the data path circuit comprising;

a defect table register to store addresses of defective multi-state memory cells in the arrays and to store replacement data bits to be written to the defective multi-state memory cells;

a working address pointer to receive and store an address of a multi-state memory cell in the arrays selected to receive one of the incoming data bits;

a defect table pointer to indicate an address in the defect table register;

a compare logic circuit to compare the working address pointer with the defect table pointer and to generate a flag if the working address pointer matches the defect table pointer, the defect table pointer being incremented in response to the generation of the flag;

a shift register to store the incoming data bits to be written to the defective multi-state memory cells as selected data bits in response to the generation of the flag and to output the selected data bits to be written to the multi-state overhead memory cells; and

a multiplex circuit to output the incoming data bits to be written to the multi-state memory cells in the arrays and to substitute the replacement data bits from the defect table register for the selected data bits to be written to the defective multi-state memory cells in the arrays.

24. The system of claim 23 wherein the data path circuit further comprises:

a host interface logic circuit to receive the incoming data bits;

a buffer circuit to store the incoming data bits;

a direct memory access circuit to transfer the incoming data bits from the buffer circuit to the multi-state memory cells in the arrays;

an ECC logic circuit to calculate check bits for the incoming data bits to be stored in the multi-state memory cells of the arrays;

a modifier logic circuit to modify the incoming data bits to be written to the multi-state memory cells of the arrays; and

wherein the multi-state memory cells comprise four-state data memory cells and four-state overhead memory cells.

25. A processing system comprising:

one or more memory devices, each memory device comprising an array of memory cells comprising data memory cells and overhead memory cells;

a controller to control read and write operations for the memory devices;

a storage medium to store addresses of defective memory cells in the arrays;

a data path circuit to receive incoming data bits to be written to the memory cells of the arrays;

means for storing the incoming data bits to be written to the defective memory cells in the arrays as selected data bits;

means for writing the selected data bits to the overhead memory cells; and

means for writing the incoming data bits to the data memory cells.

26. A method comprising:

receiving incoming data bits to be written to an array of memory cells, and receiving addresses of memory cells in the array to which the incoming data bits are to be written;

comparing the addresses of memory cells with addresses of defective memory cells in the array;

storing selected ones of the incoming data bits to be written to the defective memory cells in the array as selected data bits;

writing the incoming data bits to data memory cells in the array; and

writing the selected data bits to overhead memory cells in the array.

27. The method of claim 26 wherein:

receiving incoming data bits further comprises;

receiving the incoming data bits in a host interface logic circuit;

storing the incoming data bits in a buffer circuit;

transferring the incoming data bits from the buffer circuit to the memory cells in the array with a direct memory access circuit;

calculating check bits for the incoming data bits in an ECC logic circuit; and

modifying the incoming data bits to be written to the memory cells of the array in a modifier logic circuit;

comparing the addresses further comprises;

storing addresses of defective memory cells in the array in a defect table register;

storing replacement data bits to be written to the defective memory cells in the array in the defect table register;

storing an address of a memory cell in the array selected to receive one of the incoming data bits in a working address pointer;

indicating an address of a defective memory cell in the defect table register with a defect table pointer;

comparing the working address pointer with the defect table pointer in a compare logic circuit;

generating a flag if the working address pointer matches the defect table pointer; and

incrementing the defect table pointer in response to the generation of the flag; and

writing the selected data bits further comprises;

storing the selected data bits a shift register in response to the generation of the flag; and

writing the selected data bits serially to multi-state overhead memory cells in the array;

writing the incoming data bits further comprises;

writing the incoming data bits to multi-state data memory cells in the array through a multiplex circuit; and

writing replacement data bits from the defect table register to defective multi-state memory cells in the array through the multiplex circuit.

28. A method comprising:

receiving incoming data bits to be written to an array of multi-state memory cells, and receiving addresses of multi-state memory cells in the array to which the incoming data bits are to be written;

comparing the addresses of multi-state memory cells with addresses of defective multi-state memory cells in the array;

storing selected ones of the incoming data bits to be written to the defective multi-state memory cells in the array as selected data bits;

writing the incoming data bits to multi-state data memory cells in the array; and

writing the selected data bits to multi-state overhead memory cells in the array.

29. The method of claim 28 wherein:

receiving incoming data bits further comprises;

receiving the incoming data bits in a host interface logic circuit;

storing the incoming data bits in a buffer circuit;

transferring the incoming data bits from the buffer circuit to the multi-state memory cells in the array with a direct memory access circuit;

calculating check bits for the incoming data bits in an ECC logic circuit; and

modifying the incoming data bits to be written to the multi-state memory cells of the array in a modifier logic circuit;

comparing the addresses further comprises;

storing addresses of defective multi-state memory cells in the array in a defect table register;

storing replacement data bits to be written to the defective multi-state memory cells in the array in the defect table register;

storing an address of a multi-state memory cell in the array selected to receive one of the incoming data bits in a working address pointer;

indicating an address of a defective multi-state memory cell in the defect table register with a defect table pointer;

comparing the working address pointer with the defect table pointer in a compare logic circuit;

generating a flag if the working address pointer matches the defect table pointer; and

incrementing the defect table pointer in response to the generation of the flag; and

writing the selected data bits further comprises;

storing the selected data bits a shift register in response to the generation of the flag; and

writing the selected data bits serially to four-state overhead memory cells in the array;

writing the incoming data bits further comprises;

writing the incoming data bits to four-state data memory cells in the array through a multiplex circuit; and

writing replacement data bits from the defect table register to defective four-state memory cells in the array through the multiplex circuit.