Space management for managing high capacity nonvolatile memory

• US 6,134,151 A
• Filed: 03/06/2000
• Issued: 10/17/2000
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Guo, Min, Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/519,226
• Time in Patent Office: 225 Days
• Field of Search: 365/185.29, 365/218, 365/185.33, 365/230.03
• US Class Current: 365/185.33
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

In accordance with an embodiment of the present invention, a method and apparatus is disclosed for use in a digital system having a host coupled to at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory devices and reads the stored digital information from the nonvolatile memory devices. The memory devices are organized into blocks of sectors of information. The method is for erasing digital information stored in the blocks of the nonvolatile memory devices and comprises assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors. The method further comprises forming `super` blocks, each `super` block comprising a plurality of blocks, identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device for erasure of the particular `super` block and erasing the first and second selected blocks of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second selected blocks, wherein the speed of erase operations in the digital system is substantially increased thereby increasing the overall performance of the digital system.

Claims

1. A method for use in a digital system having a host coupled to at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory devices and reading the stored digital information from the nonvolatile memory devices, the memory devices being organized into blocks of sectors of information, the method for erasing digital information stored in the blocks of the nonvolatile memory devices and comprising:

a. assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors;

b. forming `super` blocks, each `super` block comprising a plurality of blocks;

c. identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device for erasure of the particular `super` block;

d. erasing the first and second selected blocks of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and

e. indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second selected blocks,

wherein the speed of erase operations in the digital system is substantially increased thereby increasing the overall performance of the digital system.

2. A method for use in a digital system as recited in claim 1 further including the steps of setting an erase counter equal to the number of blocks within a `super` block and decrementing the erase counter after each of the initiating steps.

3. A method for use in a digital system as recited in claim 1 further including the steps of first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof and second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof.

4. A method for use in a digital system as recited in claim 3 wherein upon the value indicated by the erase counter reaching `0`, checking for completion of the erasure of all of the blocks within the particular `super` block.

5. A method for use in a digital system as recited in claim 1 wherein during the indicating step, setting a Ready/Busy* signal for indicating that the nonvolatile memory unit is busy upon starting the erase operation on the first nonvolatile memory device and upon completion of the erase operation on the last nonvolatile memory device of the nonvolatile memory unit, resetting the Ready/Busy* signal for indicating that the nonvolatile memory unit is no longer busy.

6. A method for use in a digital system as recited in claim 1 further including the step of completing erasing of all of the selected blocks within the particular `super` block and thereafter verifying successful completion of the selected blocks of the particular `super` block.

7. A method for use in a digital system as recited in claim 6 wherein said verifying step includes the step of issuing a read status command.

8. A method for use in a digital system as recited in claim 1 wherein the particular `super` block includes more than two blocks and the method further includes the steps of selecting the more than two blocks for erasure thereof, erasing the same and upon completion of the erasure, verifying the erasure.

9. A digital system including a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory devices and reading the stored digital information from the nonvolatile memory devices, the memory devices being organized into blocks of sectors of information, the digital system comprising:

a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory devices based upon the host address information, the space manager for assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, for forming `super` blocks, each `super` block having a plurality of blocks and wherein blocks of the same sequential number in each of the nonvolatile memory devices are in like position relative to each other, the space manager circuit further for identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasing the first and second blocks so that erasure of the second block is performed without waiting for completion of the erasure of the first block, and for indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second selected blocks,

wherein the speed of erase operations is substantially increased thereby increasing the overall performance of the digital system.

10. A digital system as recited in claim 9 including a flag field for indicating the status of the particular `super` block for use in identifying the particular `super` block as being `old` and ready for erasure thereof.

11. A digital system as recited in claim 10 further including an erase counter and for setting the erase counter equal to the number of blocks within a `super` block prior to the start of the erase operation on the particular `super` block and decrementing the erase counter after starting erasure of the blocks of the particular `super` block.

12. A digital system as recited in claim 10 wherein the space manager circuit further for first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof and for second selecting the second block within the second nonvolatile memory device for erasure thereof.

13. A digital system as recited in claim 9 wherein the nonvolatile memory devices are flash chips.

14. A method for use in a digital system having a host coupled to a nonvolatile memory device, the host for storing digital information in the nonvolatile memory device and reading the stored digital information from the nonvolatile memory device, the memory unit being organized into blocks of sectors of information, the method for erasing digital information stored in the blocks of the nonvolatile memory device and comprising:

a. assigning a predetermined number of blocks, in sequential order, to the nonvolatile memory device, each block having a predetermined number of sectors;

b. forming `super` blocks, each `super` block comprising a plurality of blocks;

c. identifying a particular `super` block having at least two blocks, a first block and a second block for erasure of the particular `super` block;

d. erasing the first and second selected blocks of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and

e. indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second selected blocks,

wherein the speed of erase operations in the digital system is substantially increased thereby increasing the overall performance of the digital system.