Sensing circuit for a memory cell array

• US 6,134,164 A
• Filed: 04/22/1999
• Issued: 10/17/2000
• Est. Priority Date: 04/22/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lattimore, George McNeil, Yeung, Gus Wai-Yan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/296,876
• Time in Patent Office: 544 Days
• Field of Search: 365/205, 365/190, 365/207, 365/204, 365/202, 365/230.6, 327/51
• US Class Current: 365/205
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.

Claims

1. A memory sensing circuit for accelerating a logic level transition of a memory bit line of a complementary bit line pair having a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:

a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and

at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition.

2. The memory sensing circuit of claim 1, further comprising:

an array column decoder having an input terminal coupled to said output terminal of said inverter circuit for decoding and for selecting a cell in an array of memory cells.

3. The memory sensing circuit of claim 1 wherein the complementary bit line pair is provided by an output terminal of an array column decoder.

4. The memory sensing circuit of claim 1, wherein the dual-rail circuit comprises:

a first transistor having a drain terminal coupled to the true bit line, a gate terminal coupled to the complementary bit line, and a source terminal for coupling to a logic level value; and

a second transistor having a drain terminal coupled to the complementary bit line, a gate terminal coupled to the true bit line, and a source terminal for coupling to said logic level value.

5. The memory sensing circuit of claim 4, wherein said first and said second transistor are pMOS transistors, and said logic level value is V_DD.

6. The memory sensing circuit of claim 1 wherein said feed-back loop transistor is an nMOS transistor having a source terminal coupled to a ground voltage.

7. A semiconductor memory circuit comprising:

at least one memory column having a plurality of memory cells, said at least one memory column having a complementary bit line pair with a true bit line and a complement bit line, each of said bit lines having a full logic swing;

a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and

at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition.

8. The semiconductor memory circuit of claim 7 further comprising:

an array column decoder having an input terminal coupled to said output terminal of said inverter for decoding and for selecting a cell of an array of memory cells.

9. The semiconductor memory circuit of claim 7 wherein the complementary bit line pair is provided by an output terminal of an array column decoder.

10. The semiconductor memory circuit of claim 7, wherein the dual-rail circuit comprises:

a first transistor having a drain terminal coupled to the true bit line, a gate terminal coupled to the complementary bit line, and a source terminal for coupling to a logic level value; and

a second transistor having a drain terminal coupled to the complementary bit line, a gate terminal coupled to the true bit line, and a source terminal for coupling to said logic level value.

11. The semiconductor memory circuit of claim 10, wherein said first and said second transistor are pMOS transistors, and said logic level value is V_DD.

12. The semiconductor memory circuit of claim 10 wherein said feed-back loop transistor is an nMOS transistor having a source terminal coupled to a ground voltage.

13. A method for accelerating a logic level transition of a memory bit line of a complementary bit line pair, the method comprising the steps of:

conditioning an electrical signal transmitted on the memory bit line with a dual-rail circuit coupled across the complementary bit line pair; and

accelerating the conditioned signal through the logic level transition with a transistor that electrically couples the memory bit line to a logic level voltage reference in response to the logic level transition.

14. The method of claim 13 wherein the dual-rail circuit comprises:

a first transistor having a drain terminal coupled to the true bit line, a gate terminal coupled to the complementary bit line, and a source terminal for coupling to a logic level value; and

a second transistor having a drain terminal coupled to the complementary bit line, a gate terminal coupled to the true bit line, and a source terminal for coupling to said logic level value.

15. The method of claim 14 wherein the first and the second transistor are pMOS transistors, and the logic level value is V_DD.

16. The method of claim 13 wherein the transistor is an nMOS transistor having a source terminal coupled to the logic-level voltage reference is a ground voltage.

17. The method of claim 16 wherein the logic-level voltage reference is a ground voltage.

18. A memory sensing circuit for a semiconductor circuit having at least one memory column with a plurality of memory cells, the at least one memory column having a complementary bit line pair with a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:

means for conditioning an electrical signal transmitted on the memory bit line; and

means for accelerating said conditioned signal through a logic level transition to a logic level voltage reference in response to said logic level transition.

19. The memory sensing circuit of claim 18 wherein said conditioning means is a dual-rail circuit coupled across the complementary bit line pair.

20. The memory sensing circuit of claim 18 wherein said accelerating means is a transistor electrically coupling said memory bit line to said logic-level voltage reference in response to said logic level transition.