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Sensing circuit for a memory cell array

  • US 6,134,164 A
  • Filed: 04/22/1999
  • Issued: 10/17/2000
  • Est. Priority Date: 04/22/1999
  • Status: Expired due to Fees
First Claim
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1. A memory sensing circuit for accelerating a logic level transition of a memory bit line of a complementary bit line pair having a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:

  • a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and

    at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition.

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