Sensing circuit for a memory cell array
First Claim
1. A memory sensing circuit for accelerating a logic level transition of a memory bit line of a complementary bit line pair having a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:
- a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and
at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition.
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Accused Products
Abstract
The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.
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Citations
20 Claims
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1. A memory sensing circuit for accelerating a logic level transition of a memory bit line of a complementary bit line pair having a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:
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a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory circuit comprising:
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at least one memory column having a plurality of memory cells, said at least one memory column having a complementary bit line pair with a true bit line and a complement bit line, each of said bit lines having a full logic swing; a dual-rail circuit to couple across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines; and at least one slew-rate acceleration circuit coupled to said dual-rail circuit such that said conditioned signal is input to said slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive said conditioned signal, and having a feed-back loop transistor having a gate terminal coupled to an output terminal of said inverter, said feed-back loop transistor being responsive to an output signal placed on said output terminal for accelerating a slew-rate of said conditioned signal undergoing a state transition. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for accelerating a logic level transition of a memory bit line of a complementary bit line pair, the method comprising the steps of:
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conditioning an electrical signal transmitted on the memory bit line with a dual-rail circuit coupled across the complementary bit line pair; and accelerating the conditioned signal through the logic level transition with a transistor that electrically couples the memory bit line to a logic level voltage reference in response to the logic level transition. - View Dependent Claims (14, 15, 16, 17)
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18. A memory sensing circuit for a semiconductor circuit having at least one memory column with a plurality of memory cells, the at least one memory column having a complementary bit line pair with a true bit line and a complement bit line, each of the bit lines having a full logic swing, the memory sensing circuit comprising:
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means for conditioning an electrical signal transmitted on the memory bit line; and means for accelerating said conditioned signal through a logic level transition to a logic level voltage reference in response to said logic level transition. - View Dependent Claims (19, 20)
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Specification