Reducing power consumption in computer memory
First Claim
1. A computer system, comprising:
- an input device;
a memory device that stores data;
a processor that receives an input signal from said input device and that accesses said memory device; and
a refresh logic that provides a periodic refresh signal to refresh said memory device, and wherein the refresh logic is capable of selectively varying the rate of the refresh signal as a function of a time the computer system has been in a reduced power mode of operation.
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Accused Products
Abstract
A computer system comprising an input/output device, a processor, a memory device, and a bridge logic device for interfacing the memory device to the processor and input/output device incorporates a refresh logic device for generating a memory refresh signal during suspend mode. Because the rate at which memory must be refreshed generally depends on the temperature of the memory device, the refresh logic varies the frequency of the refresh signal according to the temperature of the memory device, resulting in substantial power savings. In a preferred embodiment, the refresh logic uses a normal-rate refresh signal at the beginning of suspend mode and incrementally steps down the refresh rate as the memory temperature decreases. In other embodiments, the refresh logic incorporates a signal generator which produces a refresh signal at a frequency that varies according the output voltage from a temperature sensor or the temperature-sensitive resistance of a thermistor. In yet another embodiment, a variable-rate refresh logic is incorporated into the memory device, resulting in a self-refreshing memory module.
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Citations
24 Claims
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1. A computer system, comprising:
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an input device; a memory device that stores data; a processor that receives an input signal from said input device and that accesses said memory device; and a refresh logic that provides a periodic refresh signal to refresh said memory device, and wherein the refresh logic is capable of selectively varying the rate of the refresh signal as a function of a time the computer system has been in a reduced power mode of operation. - View Dependent Claims (2, 3)
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4. A computer system comprising:
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an input device; a memory device that stores data; a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device; and a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time; wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses; and wherein said refresh logic comprises a counter which generates a select signal when the first predetermined time period has expired, the select signal causing said refresh logic to provide the refresh signal at the second refresh rate. - View Dependent Claims (5)
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6. A computer system comprising:
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an input device; a memory device that stores data; processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device; and a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time; wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses; and wherein said refresh logic provides the refresh signal at the second refresh rate for a second predetermined period of time and provides the refresh signal at a third refresh rate after the second predetermined time period elapses. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A computer system comprising:
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an input device; a memory device that stores data; a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time; a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device, wherein said processor asserts a select signal to said refresh logic to cause said refresh logic to vary the refresh rate; and a counter which asserts an interrupt signal to said processor after a predetermined period of time, said interrupt signal causing said processor to assert said select signal. - View Dependent Claims (13)
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14. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes after a predetermined period of time following the onset of suspend mode, comprising:
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a counter that asserts a select signal at said predetermined period of time to cause the refresh rate to change; and a refresh generator that provides the refresh signal at a particular rate based on the value of the select signal.
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15. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes after a predetermined period of time following the onset of suspend mode, comprising:
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refresh timer that provides the refresh signal before the predetermined period of time; and a divide-by-two unit coupled to said refresh timer and that provides the refresh signal after the predetermined period of time.
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16. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes at each of a plurality of predetermined time periods, comprising:
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a counter that generates select signals at said predetermined time periods, the state of the select signals determining the refresh rate; and a switch that chooses one of a plurality of refresh rates based on the state of the select signals.
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17. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes at each of a plurality of predetermined time periods, comprising:
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a frequency divider which receives a timing signal and generates a plurality of divided output signals, wherein each of the divided output signals has a different rate; and a switch, whereby said refresh logic chooses between the divided output signals to select the refresh signal.
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18. A memory device comprising:
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a refresh logic unit that provides an internal refresh signal having a variable refresh frequency; and a switch through which said memory device receives a select signal and an external refresh signal; wherein said memory device uses the internal refresh signal to refresh memory if the select signal is asserted and uses the external refresh signal to refresh memory if the select signal is deasserted.
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19. A method for refreshing a memory device in a computer system, comprising:
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(a) refreshing said memory device at an initial rate for a first predetermined period of time after initiation of a reduced power mode of operation of the host computer system; and (b) refreshing said memory device at a second rate after the first predetermined period of time. - View Dependent Claims (20, 21, 22)
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23. In a computer system having a processor receiving input signals from an input device and a memory device that stores data, a method of reducing power consumption in the computer system comprising:
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operating the computer system in a low power mode of operation, and while the computer system is in a low power mode of operation; providing a periodic refresh signal to the memory device; and slowing the rate of the periodic refresh signal to slow the refresh rates of the memory device as the memory device becomes able to retain data with a slower refresh rate.
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24. A computer system, comprising:
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an input device; a memory device that stores data; a processor that receives an input signal from an input device and that accesses said memory device; and a refresh logic adapted to provide a refresh signal to refresh said memory device, wherein the refresh logic is further adapted to vary the rate of the refresh signal based on a selected parameter after the computer system is placed in a suspend mode.
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Specification