Reducing power consumption in computer memory

• US 6,134,167 A
• Filed: 06/04/1998
• Issued: 10/17/2000
• Est. Priority Date: 06/04/1998
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Atkinson, Lee W.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/090,426
• Time in Patent Office: 866 Days
• Field of Search: 365/222, 365/228, 365/229, 711/106
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations

Abstract

A computer system comprising an input/output device, a processor, a memory device, and a bridge logic device for interfacing the memory device to the processor and input/output device incorporates a refresh logic device for generating a memory refresh signal during suspend mode. Because the rate at which memory must be refreshed generally depends on the temperature of the memory device, the refresh logic varies the frequency of the refresh signal according to the temperature of the memory device, resulting in substantial power savings. In a preferred embodiment, the refresh logic uses a normal-rate refresh signal at the beginning of suspend mode and incrementally steps down the refresh rate as the memory temperature decreases. In other embodiments, the refresh logic incorporates a signal generator which produces a refresh signal at a frequency that varies according the output voltage from a temperature sensor or the temperature-sensitive resistance of a thermistor. In yet another embodiment, a variable-rate refresh logic is incorporated into the memory device, resulting in a self-refreshing memory module.

Claims

1. A computer system, comprising:

an input device;

a memory device that stores data;

a processor that receives an input signal from said input device and that accesses said memory device; and

a refresh logic that provides a periodic refresh signal to refresh said memory device, and wherein the refresh logic is capable of selectively varying the rate of the refresh signal as a function of a time the computer system has been in a reduced power mode of operation.

2. A computer system as in claim 1 wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses.

3. A computer system as in claim 1 wherein said processor asserts a select signal to said refresh logic to cause said refresh logic to vary the refresh rate.

4. A computer system comprising:

an input device;

a memory device that stores data;

a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device; and

a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;

wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses; and

wherein said refresh logic comprises a counter which generates a select signal when the first predetermined time period has expired, the select signal causing said refresh logic to provide the refresh signal at the second refresh rate.

5. A computer system as in claim 4 wherein said refresh logic includes a divide-by-two unit receiving a timing signal and generating a divided output signal, wherein said refresh logic selects the timing signal as the refresh signal at the first refresh rate and selects the divided output signal as the refresh signal at the second refresh rate.

6. A computer system comprising:

an input device;

a memory device that stores data;

processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device; and

a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;

wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses; and

wherein said refresh logic provides the refresh signal at the second refresh rate for a second predetermined period of time and provides the refresh signal at a third refresh rate after the second predetermined time period elapses.

7. A computer system as in claim 6 wherein said refresh logic comprises a counter which generates select signals to indicate when the first and second predetermined time periods have expired, and wherein the state of the select signals encodes the refresh rate.

8. A computer system as in claim 7 wherein said refresh logic includes at least one frequency divider receiving a timing signal and generating a first divided output signal and second divided output signal having different rates, and wherein said refresh logic chooses between the timing signal, the first divided output signal, and the second divided output signal to refresh said memory device based on the state of the select signals.

9. A computer system as in claim 6 wherein said refresh logic provides the refresh signal at the third refresh rate for a third predetermined period of time and provides the refresh signal at a fourth refresh rate after the third predetermined time period elapses.

10. A computer system as in claim 9 wherein said refresh logic comprises a counter which generates select signals to indicate when the first, second, and third predetermined time periods have expired, the state of the select signals determining the refresh rate.

11. A computer system as in claim 10 wherein said refresh logic includes at least one frequency divider receiving a timing signal and generating a plurality of divided output signals having different rates, and wherein said refresh logic chooses either the timing signal or one of said plurality of divided output signals to refresh said memory device based on the state of the select signals.

12. A computer system comprising:

an input device;

a memory device that stores data;

a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;

a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device, wherein said processor asserts a select signal to said refresh logic to cause said refresh logic to vary the refresh rate; and

a counter which asserts an interrupt signal to said processor after a predetermined period of time, said interrupt signal causing said processor to assert said select signal.

13. A computer system as in claim 12 wherein said refresh logic device comprises a divide-by-two unit providing an output signal at a lower rate than the refresh rate, said refresh logic device choosing the output signal of the divide-by-two unit as the refresh signal if the select signal is asserted by the processor.

14. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes after a predetermined period of time following the onset of suspend mode, comprising:

a counter that asserts a select signal at said predetermined period of time to cause the refresh rate to change; and

a refresh generator that provides the refresh signal at a particular rate based on the value of the select signal.

15. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes after a predetermined period of time following the onset of suspend mode, comprising:

refresh timer that provides the refresh signal before the predetermined period of time; and

a divide-by-two unit coupled to said refresh timer and that provides the refresh signal after the predetermined period of time.

16. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes at each of a plurality of predetermined time periods, comprising:

a counter that generates select signals at said predetermined time periods, the state of the select signals determining the refresh rate; and

a switch that chooses one of a plurality of refresh rates based on the state of the select signals.

17. A refresh logic adapted to provide a refresh signal to memory during suspend mode in a microprocessor-based system, said refresh logic capable of selectively varying the rate of the refresh signal as a function of time such that the refresh rate changes at each of a plurality of predetermined time periods, comprising:

a frequency divider which receives a timing signal and generates a plurality of divided output signals, wherein each of the divided output signals has a different rate; and

a switch, whereby said refresh logic chooses between the divided output signals to select the refresh signal.

18. A memory device comprising:

a refresh logic unit that provides an internal refresh signal having a variable refresh frequency; and

a switch through which said memory device receives a select signal and an external refresh signal;

wherein said memory device uses the internal refresh signal to refresh memory if the select signal is asserted and uses the external refresh signal to refresh memory if the select signal is deasserted.

19. A method for refreshing a memory device in a computer system, comprising:

(a) refreshing said memory device at an initial rate for a first predetermined period of time after initiation of a reduced power mode of operation of the host computer system; and

(b) refreshing said memory device at a second rate after the first predetermined period of time.

20. A method as in claim 19 further including:

(c) generating an initial signal having an initial rate;

(d) generating a second signal having a second rate;

(e) counting until the first predetermined period of time elapses;

(f) refreshing said memory device with the initial signal before the first predetermined period of time elapses; and

(g) refreshing said memory device with the second signal after said first predetermined period of time elapses.

21. A method as in claim 20 further including generating the second signal by sending the initial signal through a frequency divider.

22. A method as in claim 19 further including changing the refresh rate at each of a plurality of predetermined time periods.

23. In a computer system having a processor receiving input signals from an input device and a memory device that stores data, a method of reducing power consumption in the computer system comprising:

operating the computer system in a low power mode of operation, and while the computer system is in a low power mode of operation;

providing a periodic refresh signal to the memory device; and

slowing the rate of the periodic refresh signal to slow the refresh rates of the memory device as the memory device becomes able to retain data with a slower refresh rate.

24. A computer system, comprising:

an input device;

a memory device that stores data;

a processor that receives an input signal from an input device and that accesses said memory device; and

a refresh logic adapted to provide a refresh signal to refresh said memory device, wherein the refresh logic is further adapted to vary the rate of the refresh signal based on a selected parameter after the computer system is placed in a suspend mode.