Semiconductor memory device

• US 6,134,169 A
• Filed: 11/22/1999
• Issued: 10/17/2000
• Est. Priority Date: 11/24/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tanaka, Hidehiko
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/447,095
• Time in Patent Office: 330 Days
• Field of Search: 365/222-236, 365/207, 365/189.04
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

In a semiconductor memory device of the present invention, a read operation is performed by activating a first word line of the plurality of word lines, transferring data read out from the memory cells simultaneously selected by the first word line via the plurality of bit line groups, latching the data from the plurality of bit line groups in the plurality of first sense amplifiers via the first switch section, transferring data from one of the plurality of first sense amplifiers to the first common data line via one of the plurality of third switch sections, and outputting the data from the first common data line to an external unit. A refresh operation is performed, simultaneously with the read operation, by activating a second word line of the plurality of word lines, and refreshing data read out from the memory cells simultaneously selected by the second word line using the plurality of second sense amplifiers via the second switch section.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells;

a plurality of word lines controlled by an output of a row decoder for selecting some of the plurality of memory cells;

a plurality of bit line groups for transferring data read out from the memory cells which are simultaneously selected by each of the plurality of word lines;

a plurality of first sense line groups connected respectively to the plurality of bit line groups via a first switch section;

a plurality of second sense line groups connected respectively to the plurality of bit line groups via a second switch section;

a plurality of first sense amplifiers connected respectively to the plurality of first sense line groups;

a plurality of second sense amplifiers connected respectively to the plurality of second sense line groups;

a plurality of third switch sections which are connected respectively to the plurality of first sense line groups and controlled by an output of a column decoder;

a first common data line connected to the plurality of third switch sections;

an input/output circuit connected to the first common data line for inputting/outputting data from/to an external unit; and

a control circuit for controlling the plurality of third switch sections so as to transfer data latched by the plurality of first sense amplifiers to the input/output circuit via the first common data line, wherein;

a read operation is performed by activating a first word line of the plurality of word lines, transferring data read out from the memory cells simultaneously selected by the first word line via the plurality of bit line groups, latching the data from the plurality of bit line groups in the plurality of first sense amplifiers via the first switch section, transferring data from one of the plurality of first sense amplifiers to the first common data line via one of the plurality of third switch sections, and outputting the data from the first common data line to an external unit; and

a refresh operation is performed, simultaneously with the read operation, by activating a second word line of the plurality of word lines, and refreshing data read out from the memory cells simultaneously selected by the second word line using the plurality of second sense amplifiers via the second switch section.

2. A semiconductor memory device according to claim 1, wherein:

the first switch section is conductive and the second switch section is non-conductive at a point in time when the first word line is selected;

after the first word line is selected, only the plurality of first sense amplifiers are activated which are connected to the plurality of first sense line groups connected to the plurality of bit line groups via the first switch section being conductive so as to amplify a potential difference between the plurality of first sense line groups and the bit line groups, thereby latching data in the plurality of first sense amplifiers;

while the data is latched in the plurality of first sense amplifiers, the first word line is unselected and data is re-written in the memory cells, the first switch section and the second switch section are turned to be non-conductive, the plurality of bit line groups separated from the plurality of first sense amplifiers and the plurality of second sense amplifiers are precharged, and the data is read out from the plurality of first sense amplifiers to the first common data line via the plurality of third switch sections, thus performing a read operation;

simultaneously with the read operation, the second switch section is turned to be conductive and a precharge circuit coupled to the bit line groups is activated so as to automatically precharge the plurality of bit line groups and the plurality of second sense line groups connected to the bit line groups; and

at a point in time when the second word line is selected, the first switch section is non-conductive and the second switch section is turned to be conductive, so that a potential difference between the plurality of first sense line groups connected to the second switch section and the bit line groups is amplified by the plurality of second sense amplifiers, thereby re-writing the data in the memory cells, after which the second word line is unselected.

3. A semiconductor memory device according to claim 1, further comprising an internal refresh counter for outputting a refresh address, wherein:

the first word line is selected based on an externally input row address; and

the second word line is selected based on the refresh address output from the internal refresh counter.

4. A semiconductor memory device according to claim 3, wherein:

the externally input row address and the refresh address output from the internal refresh counter are compared with each other;

if the addresses do not coincide with each other, the second word line is selected based on the refresh address; and

if the addresses coincide with each other, the refresh address is updated, and then the second word line is selected based on the updated refresh address.

5. A semiconductor memory device according to claim 1, wherein:

the plurality of second sense line groups are connected to the second common data line via a fourth switch section; and

the semiconductor memory device further comprises a control circuit for controlling the fourth switch section so that data latched in the plurality of second sense amplifiers is output to the external unit via the second common data line.