Configurable memory block

• US 6,134,181 A
• Filed: 02/24/1999
• Issued: 10/17/2000
• Est. Priority Date: 02/24/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc., Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Landry, Greg J.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/257,468
• Time in Patent Office: 601 Days
• Field of Search: 365/233, 365/230.03
• US Class Current: 365/233.16
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.

Claims

1. A circuit comprising:

a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals;

a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and

an output circuit configured to present an output having a variable word-width in response to said control signal.

2. The circuit according to claim 1, wherein said output circuit is further configured to present either a synchronous or an asynchronous output in response to (i) said clock signal, (ii) said control signal and (iii) data read from one or more of said plurality of storage elements.

3. The circuit according to claim 1, further comprising:

an address transition detect circuit configured to precharge a number of bitlines in response to a transition of one of said plurality of internal address signals.

4. The circuit according to claim 1, further comprising a plurality of bitline loads, each connected to one of a plurality of bitline pairs, wherein said bitline loads reduce the DC power consumed by the circuit.

5. The circuit according to claim 4, wherein each of said bitline loads comprises a half-latch.

6. The circuit according to claim 4, wherein each of said bitline loads comprises a first and a second cross-coupled gate.

7. The circuit according to claim 4, wherein each of said bitline loads comprises (i) a half-latch and (ii) a first and a second cross-coupled gate.

8. The circuit according to claim 4, wherein said bitline loads reduce the DC power to a zero standby current.

9. The circuit according to claim 4, wherein said bitlines have a full rail switching.

10. The circuit according to claim 1, wherein said circuit comprises an embedded memory.

11. The circuit according to claim 4, further comprising a plurality of data buffers each connected to one of said bitline pairs.

12. The circuit according to claim 4, further comprising a plurality of data line equalization circuits each coupled to one of a number of data line pairs.

13. The circuit according to claim 12, further comprising a data output circuit configured to present a data output in response to said first and second outputs of a data buffer.

14. The circuit according to claim 1, wherein said circuit operates as a random access memory (RAM), read only memory (ROM) or a logic circuit, in response to said control signal.

15. The circuit according to claim 1, wherein said circuit further comprises a plurality of bitline loads, an equalization circuit, a data buffer circuit, a data line equalization circuit and a data output circuit, each fabricated using CMOS transistors.

16. A circuit comprising:

means for storing data in a plurality of storage elements in response to one of a plurality of internal address signals;

means for generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and

means for generating an output having a variable wordwidth in response to said control signal.

17. A method for reading and writing data to a plurality of storage elements comprising the steps of:

(A) configuring each of said storage elements to store data in response to one of a plurality of internal address signals;

(B) generating each of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and

(C) generating an output having a variable word-width in response to said control signal.

18. The method according to claim 17, further comprising the step of:

(D) precharging a number of bitlines in response to a transition of one of said internal address signals.

19. The method according to claim 17, wherein said plurality of storage elements can be configured as a random access memory (RAM), read only memory (ROM) or a logic circuit, in response to said control signal.

20. An apparatus comprising:

a memory comprising a plurality of storage elements each configured to store data in response to one of a plurality of internal address signals;

a plurality of address circuits each configured to generate one of said plurality of internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal; and

an address transition detect circuit configured to precharge a number of bitlines in response to a transition of one of said plurality of internal address signals.