Cycle independent data to echo clock tracking circuit

• US 6,134,182 A
• Filed: 10/19/1999
• Issued: 10/17/2000
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pilo, Harold, Covino, James J.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/420,694
• Time in Patent Office: 364 Days
• Field of Search: 365/233, 365/194
• US Class Current: 365/233.11
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.

Claims

1. A memory system for a high speed double data rate (DDR) memory which generates a data signal and an echo clock signal, comprising:

a memory controller clocked by a master clock signal;

a random access memory (RAM) array receiving input from said memory controller and outputting a global data signal;

a comparator for receiving the global data signal and the master clock signal to determine a delay timing there between; and

a variable delay circuit for receiving said delay timing signal and generating a delayed pipelined clock signal for simultaneously latching out said data signal and said echo clock signal.

2. A memory system for a high speed double data rate (DDR) memory as recited in claim 1 wherein said RAM array comprises static random access memory (SRAM) devices.

3. A memory system for a high speed double data rate (DDR) memory as recited in claim 1 wherein said RAM array comprises dynamic random access memory (DRAM) devices.

4. A memory system for a high speed double data rate (DDR) memory as recited in claim 1 wherein said comparator comprises:

means for generating a stop signal on a rising master clock edge and a reset signal on a falling master clock edge; and

a plurality of latches connected in series, a first latch in said series receiving said global data signal, wherein said latches are reset by said reset signal and thereafter said latches sequentially output a plurality of DELAY signals in accordance with a presence of said global data signal until said stop signal is received.

5. A memory system for a high speed double data rate (DDR) memory as recited in claim 4 further comprising a register for storing said DELAY signals.

6. A memory system for a high speed double data rate (DDR) memory as recited in claim 4 wherein said variable delay circuit comprises:

a plurality of delay buffers connected in series for delaying said master clock signal;

a plurality of logic gates for enabling a plurality of variable delay paths, each of said logic gates having a first input connected to sequential ones of said delay buffers and a second input connected to receive one of said plurality of DELAY signals; and

a delayed pipelined clock driver for outputting a pipelined CLKRISE/CLKFALL signal in accordance with said enabled variable delay paths.

7. A memory system for a high speed double data rate (DDR) memory as recited in claim 6 further comprising a fast path for immediately outputting said pipelined CLKRISE/CLKFALL signal if said comparator determines no delay is required.