Oscillator for measuring on-chip delays
First Claim
1. An oscillator comprising:
- a. a multiplexer having first and second multiplexer input terminals, a select terminal, and a multiplexer output terminal connected to the select terminal;
b. a first signal path having;
i. an inverter having;
(1) an inverter input terminal connected to the multiplexer output terminal; and
(2) an inverter output terminal; and
ii. a test circuit having;
(1) a test-circuit input terminal connected to the inverter output terminal; and
(2) a test-circuit output terminal connected to the first multiplexer input terminal;
wherein the test circuit delays high-to-low signal transitions by a first delay period and delays low-to-high signal transitions by a second delay period; and
c. a second signal path having a second input terminal connected to the multiplexer output terminal and a second output terminal connected to the second multiplexer input terminal.
1 Assignment
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Accused Products
Abstract
A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish a worst-case delay for the signal path. The worst-case delay can be used, in turn, to create accurate timing specifications for logic circuits that include similar or identical signal paths. To determine the delay through the signal path, the signal path is used with a second, typically identical, signal path to create alternating feedback paths of an oscillator. The oscillator is configured to output a test-clock signal having a period proportional to either the rising- or falling-edge delays through the two signal paths. The test-signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the signal path of interest.
49 Citations
19 Claims
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1. An oscillator comprising:
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a. a multiplexer having first and second multiplexer input terminals, a select terminal, and a multiplexer output terminal connected to the select terminal; b. a first signal path having; i. an inverter having; (1) an inverter input terminal connected to the multiplexer output terminal; and (2) an inverter output terminal; and ii. a test circuit having; (1) a test-circuit input terminal connected to the inverter output terminal; and (2) a test-circuit output terminal connected to the first multiplexer input terminal; wherein the test circuit delays high-to-low signal transitions by a first delay period and delays low-to-high signal transitions by a second delay period; and c. a second signal path having a second input terminal connected to the multiplexer output terminal and a second output terminal connected to the second multiplexer input terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A system comprising:
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a. a test oscillator configured to produce a test clock comprised of alternating falling and rising signal transitions on a test-clock output terminal, the test oscillator including; i. a multiplexer having first and second multiplexer input terminals, a select terminal, and a multiplexer output terminal connected to the select terminal and to the test-clock output terminal; ii. a first signal path having a first input terminal connected to the multiplexer output terminal and a first output terminal connected to the first multiplexer input terminal; and iii. a second signal path having a second input terminal connected to the multiplexer output terminal and a second output terminal connected to the second multiplexer input terminal; and b. a counter having a counter input terminal connected to the test-clock output terminal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification