Method for lowpass filter calibration in a satellite receiver

• US 6,134,282 A
• Filed: 06/18/1997
• Issued: 10/17/2000
• Est. Priority Date: 06/18/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Keate, Christopher, Ben-Efraim, Nadav
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): PHU, PHUONG M
• Application Number:
  US08/878,329
• Time in Patent Office: 1,217 Days
• Field of Search: 375/316, 375/343, 375/344, 375/350, 455/266, 455/340, 455/3.2
• US Class Current: 375/350
• CPC Class Codes: H03J 3/08 by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 7/065 the counter or frequency divider being used in a phase locked loop
• CPC Class Codes: H03J 7/08 using varactors, i.e. voltage variable reactive diodes H03J7/06 takes precedence
• CPC Class Codes: H04B 1/1027 assessing signal quality or detecting noise/interference for the received signal
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2001/1054 by changing bandwidth
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04H 40/90 specially adapted for satellite broadcast receiving

Abstract

An improved satellite receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip includes a lowpass filter having a configurable cutoff frequency, and the tuner chip uses a frequency signal to provide accurate adjustment of the cutoff frequency. A clock signal having a clock frequency is converted into a control voltage which determines the cutoff frequency of the lowpass filter. Consequently, the cutoff frequency may be increased by increasing the clock frequency, or decreased by decreasing the clock frequency. This configuration provides for improved cutoff frequency control in the presence of signal interference.

Claims

1. A DBS receiver front end comprising:

a tuner chip having a lowpass filter with a configurable cutoff frequency, wherein the tuner is configured to adjust the cutoff frequency based on a clock signal frequency of a clock signal, wherein the tuner chip is further configured to receive a receive signal, to convert the receive signal to a product signal, and to filter the product signal with the lowpass filter to provide a baseband signal; and

a demodulator/decoder chip coupled to receive the baseband signal and configured to convert the baseband signal to a decoded signal, wherein the demodulator/decoder chip is further configured to provide said clock signal,

wherein the tuner chip further comprises a frequency-to-voltage converter coupled to convert the clock signal frequency into a control voltage which is applied to the lowpass filter to adjust the cutoff frequency.

2. The DBS receiver front end of claim 1, wherein the frequency-to-voltage converter comprises:

a bandpass filter coupled to provide a frequency-dependent phase shift to the clock signal to produce a phase shifted signal; and

a mixer coupled to combine the phase shifted signal with the clock signal to produce the control voltage.

3. A DBS receiver front end comprising:

a tuner chip having a lowpass filter with a configurable cutoff frequency, wherein the tuner is configured to adjust the cutoff frequency based on a clock signal frequency of a clock signal, wherein the tuner chip is further configured to receive a receive signal, to convert the receive signal to a product signal, and to filter the product signal with the lowpass filter to provide a baseband signal; and

a demodulator/decoder chip coupled to receive the baseband signal and configured to convert the baseband signal to a decoded signal, wherein the demodulator/decoder chip is further configured to provide said clock signal,

wherein the demodulator/decoder chip further comprises;

a crystal oscillator configured to provide a timing signal having a crystal resonance frequency;

a programmable divider coupled to receive the timing signal, wherein the programmable divider is configured to provide said clock signal by dividing the crystal resonance frequency by an adjustable constant.

4. The DBS receiver front end of claim 3, wherein the demodulator/decoder chip further comprises a microcontroller configured to set the adjustable constant to provide a desired reception bandwidth.

5. The DBS receiver front end of claim 4, wherein the microcontroller is further configured to set a program counter to provide a desired reception frequency.

6. The DBS receiver front end of claim 3, wherein the demodulator/decoder chip further comprises:

an analog-to-digital converter coupled to convert the baseband signal into a digital baseband signal;

a filter coupled to filter the digital baseband signal to produce a filtered signal, wherein the filter is configured to maximize a signal to noise ratio of the filtered signal;

a decoder coupled to convert the filtered signal into said decoded signal.

7. A tuner configured to receive a receive signal and convert the receive signal into a baseband signal, wherein the tuner comprises:

a lowpass filter with an adjustable cutoff frequency to control a bandwidth of the baseband signal, wherein the cutoff frequency is determined by a control voltage;

a frequency-to-voltage converter configured to receive a clock signal having a clock signal frequency, wherein the frequency to voltage converter is further configured to convert the clock signal frequency into the control voltage.

8. The tuner of claim 7, wherein the frequency-to-voltage converter comprises:

a bandpass filter coupled to provide a frequency-dependent phase shift to the clock signal to produce a phase shifted signal; and

a mixer coupled to combine the phase shifted signal with the clock signal to produce the control voltage.

9. The tuner of claim 7, wherein said baseband signal comprises an in-phase signal component and quadrature-phase signal component, and wherein the tuner further comprises:

an I/Q downconverter coupled receive the receive signal and a tuning frequency signal, wherein the I/Q downconverter is configured to responsively provide a first product signal and a second product signal to the lowpass filter;

a gain control amplifier coupled to receive the baseband signal components from the lowpass filter, wherein the gain control amplifier multiplies the baseband signal components by an adjustable gain to produce constantmaximum baseband signal components.

10. The tuner of claim 9, wherein the I/Q downconverter comprises:

a phase-shift network which converts the tuning frequency signal into a zero-phase signal and a 90-degree-phase signal;

a first mixer coupled to combine the zero-phase signal with the receive signal to provide the first product signal; and

a second mixer coupled to combine the 90-degree-phase signal with the receive signal to provide the second product signal.

11. A method for converting a receive signal to a baseband signal, wherein the method comprises:

setting a tuning frequency signal to indicate a desired reception frequency;

providing a clock signal frequency of a clock signal to indicate a desired reception bandwidth;

determining a lowpass filter cutoff frequency from said clock signal frequency;

receiving the receive signal;

combining the tuning frequency signal with the receive signal to produce a product signal; and

lowpass filtering the product signal to attenuate signal energy above the cutoff frequency, wherein said determining comprises;

filtering the clock signal to produce a phase shifted signal;

mixing the phase shifted signal with the clock signal to produce a mixed signal; and

lowpass filtering the mixed signal to produce a cutoff frequency control voltage.

12. A method for converting a receive signal to a baseband signal, wherein the method comprises:

setting a tuning frequency signal to indicate a desired reception frequency;

providing a clock signal frequency of a clock signal to indicate a desired reception bandwidth;

determining a lowpass filter cutoff frequency from said clock signal frequency;

receiving the receive signal;

combining the tuning frequency signal with the receive signal to produce a product signal; and

lowpass filtering the product signal to attenuate signal energy above the cutoff frequency, wherein said providing comprises;

receiving a crystal oscillation signal;

counting cycles in the crystal oscillation signal with a counter; and

restarting the counter when a programmable value is reached.