Redefinable signal processing subsystem

• US 6,134,605 A
• Filed: 04/15/1998
• Issued: 10/17/2000
• Est. Priority Date: 04/15/1998
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Diamond Multimedia Systems Incorporated (SONICblue Incorporated)
• Inventors: Hudson, Michael, Moore, Daniel L.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/060,745
• Time in Patent Office: 916 Days
• Field of Search: 710/8-19, 710/62, 710/72-74, 710/260, 712/37, 712/232, 714/1, 714/2, 714/100, 714/30, 348/57, 709/301-303
• US Class Current: 710/13
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function by attaching a function-specific module to the redefinable subsystem and downloading function-defining code into the subsystem. The redefinable subsystem includes at least a DSP, a local memory interface, a host interface, and a function module interface. The function-specific module includes at least a subsystem interface, an identifier storage unit, a signal format converter, and a communication adapter. In operation, after a function-specific module is coupled to the subsystem, the subsystem receives a function identifier from the identifier storage unit on the module. The subsystem then requests and receives function-defining code from a host. The function-defining code is maintained in an auxiliary memory and portions thereof are periodically distributed to a local memory, coupled to the subsystem via the local memory interface, at which time the code modules are available for execution by the DSP. When engaged in communications, the module receives data from the DSP through a high speed digital serial channel. The module converts the data format with its signal format converter and then passes the converted data to the communication adapter. The communication adapter conditions the data for conveyance to an external communication signal delivery media.

Claims

1. A functionally redefineable signal processing subsystem, comprising:

a) a module interface supporting a function-specific module;

b) a DSP in communication with said module interface for communicating data between said subsystem and said function-specific module;

c) a host interface supporting a host, said host interface for receiving function-defining code corresponding to said function-specific module from said host, said function-defining code stored in an auxiliary memory;

d) a DSP local memory interface, in communication with said DSP and coupleable to a local memory, said local memory for storing a replaceable portion of said function code, said replaceable portion of said function-specific code available for execution by said DSP.

2. The functionally redefineable signal processing subsystem of claim 1, further including an auxiliary memory interface coupleable to said auxiliary memory.

3. The functionally redefineable signal processing subsystem of claim 2, wherein said auxiliary memory interface includes a DRAM interface.

4. The functionally redefineable signal processing subsystem of claim 2, wherein said auxiliary memory interface includes a SRAM interface.

5. The functionally redefineable signal processing subsystem of claim 2, wherein said auxiliary memory interface includes a disk drive interface.

6. The functionally redefineable signal processing subsystem of claim 1, wherein said function-defining code is stored in said auxiliary memory located on said host.

7. The functionally redefineable signal processing subsystem of claim 1, further including said auxiliary memory.

8. The functionally redefineable signal processing subsystem of claim 1, further including a RISC processor.

9. The functionally redefineable signal processing subsystem of claim 1, wherein said local memory interface includes an SRAM interface.

10. The functionally redefineable signal processing subsystem of claim 1, wherein said module interface includes:

a plurality of high speed digital serial data channels; and

at least one module identification line for carrying a module identifier signal.

11. The functionally redefineable signal processing subsystem of claim 10, wherein said module interface further includes:

a low speed serial channel, said low speed serial channel including said at least one module identification line;

a mid-speed serial channel; and

general purpose I/O lines.

12. The functionally redefineable signal processing subsystem of claim 11, wherein said low speed serial channel is a Microwire channel.

13. The functionally redefineable signal processing subsystem of claim 11, wherein said mid-speed serial channel is a PCM codec interface.

14. The functionally redefineable signal processing subsystem of claim 11, wherein said mid-speed serial channel is an Audio Codec '"'"'97 interface.

15. A functionally redefineable signal processing system, comprising:

a) a module interface supporting a function-specific module;

b) a DSP in communication with said module interface for communicating data between said subsystem and said function-specific module;

c) an auxiliary memory for maintaining function-defining code including a plurality of code modules;

d) a DSP memory operatively coupled to said DSP for replaceably storing a code module, thereby availing said code module for execution by said DSP;

e) a processor for directing the loading of said code modules into said DSP memory.

16. The functionally redefineable signal processing system of claim 15, further including a host interface supporting a host and for receiving said function-defining code.

17. The functionally redefineable signal processing system of claim 16, further including said host, wherein said auxiliary memory and said processor reside on said host.

18. The functionally redefineable signal processing system of claim 15, wherein:

said auxiliary memory includes a DRAM;

said DSP memory includes an SRAM; and

said processor includes a RISC processor.

19. The functionally redefineable signal processing system of claim 15, wherein said module interface includes:

a plurality of high speed digital serial channels;

a Microwire channel, said Microwire channel including at least one line for receiving a module identifier [indentifier];

a mid-speed serial channel; and

general purpose I/O lines.

20. The functionally redefineable signal processing system of claim 19, wherein said mid-speed serial channel is an Audio Codec '"'"'97 interface.

21. A functionally redefineable signal processing subsystem, comprising:

a bus;

a microprocessor having access to said bus;

a plurality of DSPs having access to said bus;

a memory interface accessible by said plurality of DSPs and said microprocessor, said memory interface couplable to a memory for storing function code;

a functional module interface accessible by said plurality of DSPs and couplable to a function module;

a host interface in communication with said bus and couplable to a host; and

a plurality of DSP local memory interfaces each respectively accessible by a respective one of said DSPs and each coupleable to a respective local memory, each said respective local memory for storing a replaceable portion of said function code.

22. The functionally redefineable signal processing subsystem of claim 21, including only one microprocessor and further including a non-volatile memory coupled to said bus to store boot code.

23. The functionally redefineable signal processing subsystem of claim 22, further including a plurality of alternatively selectable host interfaces.

24. The functionally redefineable signal processing subsystem of claim 22, further including said memory for storing function code and said local memory.

25. A functionally redefineable signal processing subsystem, comprising:

a bus;

a single RISC processor having access to said bus;

a plurality of DSPs having access to said bus;

a memory interface accessible by said plurality of DSPs and said RISC processor, said memory interface coupleable to a memory for storing function code;

a serial functional module interface at least partially accessible by said plurality of DSPs and coupleable to a function module;

a host interface operatively coupled to said bus and coupleable to a host;

a plurality of DSP local memory interfaces each respectively accessible by a respective one of said DSPs and each coupleable to a respective local memory, each said respective local memory for storing a replaceable portion of said function code;

a non-volatile memory coupled to said bus and storing subsystem boot code.

26. The functionally redefineable signal processing subsystem of claim 25, further including:

a plurality of alternatively selectable interfaces to a host, said interfaces operatively coupled to said bus.

27. The functionally redefineable signal processing subsystem of claim 25, further including:

said memory for storing function code and said local memory.

28. A functionally redefineable signal processing subsystem, comprising:

a bus;

a DSP having access to said bus;

a host interface in communication with said bus and coupleable to a host system having a host processor and a host memory for storing functionally selectable code, said host processor having access to said bus and said DSP having access to said host memory;

a local memory interface coupleable to a local memory, said local memory for storing a selected portion of said functionally selectable code, said local memory interface accessible by said DSP and by said host processor;

a serial function module interface coupleable to a function-specific module, said function module interface accessible by said DSP, said function module interface including a module identification line for carrying a signal that identifies said functionally selectable code.

29. The functionally redefineable signal processing subsystem of claim 28, further comprising:

said local memory.

30. The functionally redefineable signal processing subsystem of claim 28, wherein said host interface is a PCI interface.

31. The functionally redefineable signal processing subsystem of claim 28, wherein said host interface is an ISA interface.

32. The functionally redefineable signal processing subsystem of claim 28, wherein said host interface is a LPC interface.