Variable slot configuration for multi-speed bus

• US 6,134,621 A
• Filed: 06/05/1998
• Issued: 10/17/2000
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Thurber, Steven Mark, Neal, Danny Marvin, Kelley, Richard Allen, Nicholson, James Otto
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US09/092,153
• Time in Patent Office: 865 Days
• Field of Search: 710/104, 710/101, 710/102, 710/103, 710/126, 710/127, 364/240, 364/240.3, 364/270, 364/270.2, 364/270.3, 713/501, 713/322, 713/500, 713/600
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.

Claims

1. A method for operating a device bus, said device bus being arranged to have a number of devices connected thereto, said device bus being arranged to be connected to a clock signal source, said clock signal source being selectively operable to provide a plurality of clock signals with each of said clock signals having a different frequency, said method comprising:

determining said number of said devices being connected to said device bus; and

applying one of said clock signals to all devices connected to said device bus, said one of said clock signals being determined depending upon said number of said circuit devices being connected to said device bus.

2. A method for operating a device bus, said device bus being arranged to have circuit devices connected thereto, said device bus being arranged to be connected to a clock signal source, said clock signal source being selectively operable to provide at least first and second clock signals at first and second frequencies, respectively, to said circuit devices connected to said device bus, said method comprising:

determining a device number, said device number being representative of a number of said circuit devices being connected to said device bus;

applying said first clock signal to all circuit devices connected to said device bus if said device number exceeds a first predetermined number; and

applying said second clock signal to all circuit devices connected to said device bus if said device number is less than a second predetermined number.

3. The method as set forth in claim 2 wherein said first frequency is less than said second frequency.

4. The method as set forth in claim 3 wherein said device bus is a PCI bus.

5. The method as set forth in claim 3 wherein said circuit devices are removable circuit cards arranged to be selectively coupled to said device bus.

6. The method as set forth in claim 5 wherein said circuit devices further include circuit embodiments which are permanently connected to said device bus.

7. The method as set forth in claim 2 and further including:

for each of said circuit devices, determining a device frequency at which said circuit devices are capable of running; and

applying said first clock signal to all circuit devices connected to said device bus if any of said circuit devices is capable of running only at said first frequency.

8. The method as set forth in claim 7 wherein said device bus includes 1st and second bus segments, each of said first and second bus segments being capable of having circuit devices connected thereto, said method further including:

selectively connecting said first bus segment to said second bus segment when said device bus is operating at said first frequency, whereby a greater number of circuit devices are selectively operated at said first frequency than a number of circuit devices capable of operating if said device bus is operated at said second frequency.

9. The method as set forth in claim 8 and further including:

selectively disconnecting said second bus segment from said first bus segment when said device bus is being operated at said second frequency, whereby relatively fewer circuit devices are operated when said device bus is operated at said second frequency.

10. The method as set forth in claim 9 wherein said first frequency is less than said second frequency.

11. The method as set forth in claim 10 wherein said device bus is a PCI bus.

12. The method as set forth in claim 11 wherein said first frequency is 33 MHz and said second frequency is 66 MHz.

13. The method as set forth in claim 7 and further including:

applying said second clock signal to all circuit devices connected to said device bus if all of said circuit devices are capable of running at said second frequency and said number of circuit devices is less than said second predetermined number.

14. The method as set forth in claim 2 wherein said step of determining is accomplished during a configuration cycle of said device bus.

15. A method for operating a device bus, said device bus being arranged to have circuit devices connected thereto, said device bus being arranged to be connected to a clock signal source, said clock signal source being selectively operable to provide at least first and second clock signals at first and second frequencies, respectively, to said circuit devices connected to said device bus, said method comprising:

configuring said device bus for operation at said first frequency;

determining that all said circuit devices connected to said device bus are capable of running at said second frequency;

determining that all of said circuit devices connected to said device bus is less than a predetermined number;

resetting said circuit devices to operate at said second frequency; and

resetting said device bus to run at said second frequency.

16. An information processing system comprising:

a CPU device;

a system bus, said CPU device being coupled to said system bus;

a device bus;

a bridge circuit connected between said system bus and said device bus, said device bus being coupled to a plurality of connection slots, said connection slots being arranged for selectively providing connection of said circuit devices to said device bus;

first detection means coupled to said connection slots, said first detection means being arranged for detecting which of said connection slots contain circuit devices;

second detection means coupled to said connection slots, said second detection means being arranged for detecting a frequency at which said circuit devices are capable of running; and

clock control means coupled to said first and second detection means and said connection slots, said clock control means being selectively operable in response to outputs from said first and second detection means for selectively applying one of first or second clock signals to said circuit devices.

17. The system as set forth in claim 16 wherein said device bus is comprised of first and second bus segments, said system further including:

a switching device connected between said first and second bus segments, said switching device being selectively operable for connecting predetermined lines of said first and second bus segments in response to outputs from said first and second detection means.